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never stop thinking. microcontrollers data sheet, v2.3, nov. 2003 tc11ib 32-bit single-chip microcontroller
edition 2003-11 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certai n components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but no t limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms a nd conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in lif e-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, v2.3, nov. 2003 never stop thinking. tc11ib 32-bit single-chip microcontroller
tc11ib advance information revision history: 2003-11 v2.3 previous version: v1.1, 2002-03 v1.2, 2002-04 v1.3, 2002-09 v2.0, 2002-12 v2.1, 2003-02 v2.2, 2003-07 page subjects (major changes since last revision) 71 power supply current is updated. we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
data sheet 1 v2.3, 2003-11 tc11ib 32-bit single-chip microcontroller tricore family advance information ? high performance 32-bit tric ore cpu with 4-stage pipeli ne running at 96mhz clock dual issue super-sca lar implementation ? mac instruction maximum triple issue circular buffer and bit-reverse ad dressing modes for dsp algorithms flexible multi-master interrupt system very fast interrupt response time hardware controlled context swit ch for task switch and interrupts windows ce compliant memo ry management unit (mmu) 64 kbyte of on-chip sram fo r data and time critical code independent peripheral control processor (pcp) for low level driver support with 20 kbyte code / parameter memory edram local memory unit (lmu) wi th 512 kbytes co de/data memory. comdram with 1mbytes dram memory high performance local memory bus (lmb) for fast access between caches and on- local memories and fast-fpi interface. two on-chip flexible peripheral interface buses (fast fpi bus an d slow fpi bus) for interconnections of functional units flexible external bus interf ace unit (ebu) used for commun ication with external data memories such as pc 100 sdram, bu rst flash and sram etc. and external peripheral units, includi ng intel style and moto rola style peripherals. on-chip peripheral units ? two multifunctional general purpose timer units (gptu0 & gptu1) with three 32- bit timer/counters each ? asynchronous/synchronous serial channe ls (asc) with irda data transmission, receive/transmit fifos, parity, fr aming and overrun error detection ? high speed synchronous serial channel s (ssc) with progra mmable data length and shift direction ? asynchronous serial interface (16x50) wi th programmable xon/xoff characters, baudrate generator, receive/transmit fifos and standard modem interface support. ? 16 mhz multimediacard interface (mmci) , a glueless interface to multimediacard bus, with bus clock gene ration, crc protection and up to 2 mbyte/s data communication. ? fast ethernet controller wi th 10/100 mbps mii-base d physical devices support. ? pci v2.2 interface with pci bus po wer management and dm a data transfer. ? watchdog timer a nd system timer six 16-bit digital i/o ports on-chip debug support (ocds)
tc11ib data sheet 2 v2.3, 2003-11 power management system clock generation unit with pll ambient temperature under bias: -25 c to +85 c p-bga-388-2 package
tc11ib data sheet 3 v2.3, 2003-11 block diagram figure 1 tc11ib block diagram mcb04939 pcp interrupt 4 k data sram 16 k code sram ocds fpi interface boot-rom 16 kbytes mmci 16x50 xon/ xoff asc fifo, irda ssc gptu1 3 timers gptu0 3 timers scu (pwr) power management, watchdog timer, reset bcu1 slow fpi bus cerberus jtag pll 96 & 48 mhz tricore 1.3 cpu interrupt trace & ocds pmu (program memory unit) 24 kb scratch pad ram 8 kb instruction cache lmu 512 kb edram jtag i/o xtal2 xtal1 5 control brkout brkin 8 ocdse ocds2 ffi bridge 16 8 dmu (data memory unit) 24 kb scratch pad ram 8 kb data cache comdram 1 mb, 96 mhz bcu0 fast fpi bus fast fpi bus 96 mhz, 32 bit lfi bridge ebu_lmb fast ethernet pci v2.2 33 mhz (dma support) + power management 8 3 2 8 3 1 port0 port1 port2 mdi o txclk rxclk 15 32 20 p_ad[31:0] p_control port3 port4 port5 9 32 33 ad[31:0] ebu_control mmu 24 a[23:0] lmb (local memory bus) 96 mhz, 64 bit 3 16 16 16 external interrupts external interrupts 16 16 16 128 64 v dd 1.8-3.3 v v ss slow fpi bus (flexible peripheral interface) 48 mhz, 32 bit tc11ib block diagram
tc11ib data sheet 4 v2.3, 2003-11 logic symbol figure 2 tc11ib logic symbol mcb04945 tc11ib port 0 16-bit svm wait rd/wr rd cpuclk cfg[0:3] nmi hdrst porst v ss v ddosc hold ras ale breq hlda ebu control alternate functions digital circuitry power supply 4 general control cas cs[0:6] 7 csemu csglb csovl csfpi cke mr_w rmw ebuclk baa adv aclk cmdelay m ii_txclk mii_rxclk mii_mdio testmode tm_ctrl1 tm_ctrl2 clk42 pll96_ctrl pll42_ctrl xtal1 xtal2 ethernet clock test v ssosc v ddpll96 v sspll96 v ddpll42 v sspll42 oscillator / pll 52 21 v dd v ddp 20 v dddram 2 v comref v lmuref p_clk33 p_idsel p_gnt p_req p_pme p_intb p_inta p_lock p_irdy p_frame p_trdy p_devsel p_stop p_perr p_serr p_par p_c/be[0:3] p_ad[0:31] ocds2brk[0:2] ocds2pc[0:7] ocds2ps[0:4] ocds/ jtag control a[0:23] bc[0:3] ad[0:31] port 1 16-bit port 2 16-bit port 3 16-bit port 4 16-bit port 5 16-bit gptu0/1 ssc0/1, mmci, asc, 16x50 ethernet, mmci external interrupts mmci ebu control ocds / jtag control pci
tc11ib data sheet 5 v2.3, 2003-11 pin configuration figure 3 tc11ib pinning: p-bga-388 package (top view) mcp04950 af 123456789 mii_ mdio 10 11 12 13 xtal2 14 15 xtal1 16 17 p2.3 18 19 20 21 baa 22 23 reser ved p1.15 hd rst a b pll96 ctrl p2.2 v dd osc c cpu clk a b c d v ss d e f g h j k l m n p r t u p3.7 v p3.8 p3.9 w f g h j k l m n p r t u v w ac e ad ad ae ae p5.0 af reser ved 1234567891011121314151617181920 242526 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss p1.13 p1.11 p1.7 p1.4 p1.0 p2.12 p2.10 mii_ txclk v dd pll42 v ss pll96 v lm u ref v dd dram p2.1 ale 24 25 26 cs glb hlda a[20] ad[31] ad[30] ad[29] a[21] ad[23] breq cmde lay csfpi adv p2.5 p2.7 v dd pll96 pll42 ctrl v dd p2.8 p2.11 p2.14 p1.1 p1.5 p1.8 v dd p1.14 ocds 2ps[2] nmi ocds 2pc[7] po rst p1.12 p1.9 p1.6 p1.2 p2.15 p2.13 p2.9 mii_ rxclk tm ctrl2 v ss pll42 v ssosc tm ctrl1 p2.6 p2.4 p2.0 wait cs ovl mr_w hold a[22] ad[22] ad[21] ad[28] ad[26] ad[27] ad[20] v ss a[23] v dd svm v ddp v ss v dd v ddp reser ved v ddp v ss clk42 v ddp v dd v ss v ddp p1.3 v dd p1.10 v ss ocds 2pc[4] ocds 2ps[1] ocds 2ps[4] ocds 2pc[3] ocds 2pc[6] ocds 2ps[0] ocds 2ps[3] ocds 2pc[1] ocds 2pc[2] ocds 2pc[5] v dd ocds 2pc[0] ocds 2brk [0] ocds 2brk [1] ocds 2brk [2] v dd ocds _e brk _in v ddp v ss brk _out cfg [3] cfg [2] p0.0 cfg [1] cfg [0] v dd p0.3 p0.2 p0.1 v ddp p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 v ddp p0.11 p0.12 p0.13 v ss p0.14 p0.15 p3.0 p3.1 p3.2 v dd p3.3 v ddp p3.4 p3.5 p3.6 v dd p3.10 p3.11 v ddp y p4.0 p4.1 p4.2 p3.12 p3.13 p3.14 p4.4 p4.5 aa ab ac p3.15 p4.3 p4.6 p4.8 p4.9 p4.7 p5.3 p5.10 v ddp v ddp p_ pme v ddp p_ idsel v ddp v ss v dd v ss v dd v ss v dd v ss v dd v dd v ss v ddp p_ stop v dd p_ad [13] v ss p_c/be [0] cs emu cs[1] y aa ab ad[24] ad[25] ad[18] ad[19] v dd ad[15] ad[16] ad[17] v ddp bc[2] ad[0] ad[1] ad[13] ad[14] ad[6] ad[7] v ddp ad[11] ad[12] ad[5] v ss ad[9] ad[10] ad[4] v dd ad[8] ad[3] ad[2] aclk bc[3] bc[0] bc[1] v ss rd/ wr cas ebu clk v ddp ras cs[6] cke a[17] a[18] a[19] cs[5] v ddp a[16] a[15] a[14] v dd a[12] a[11] a[13] v ss a[1] a[9] a[10] v ddp a[2] a[7] a[8] cs[4] a[3] a[4] a[6] v dd cs[3] a[5] a[0] cs[0] cs[2] rmw rd 21 22 23 p4.10 p4.11 p4.14 p5.2 p5.6 p5.9 p5.13 tms tdi vcom ref p_ gnt p_ad [30] p_ad [28] p_ad [26] p_ad [22] p_ad [20] p_ad [18] p_ frame p_ trdy p_ par p_ad [15] p_ad [11] p_ad [9] p_ad [6] p_ad [2] p_ad [0] p4.12 p4.13 p5.1 p5.5 p5.8 p5.12 p5.15 trst test mode p_ in ta p_ req p_ad [29] p_ad [27] p_ad [24] p_ad [23] p_ad [19] p_ad [16] p_ irdy p_ lock p_ serr p_ad [14] p_ad [10] p_ad [7] p_ad [4] p_ad [1] reser ved p_c/be [1] p_ad [12] p_ad [8] p_ad [5] p_ad [3] p_ perr p_dev sel p_c/be [2] p_ad [25] p_ad [21] p_ad [17] p_c/be [3] v dd dram p_ad [31] p_clk 33 p_ in tb reser ved tdo tck p4.15 p5.4 p5.7 p5.11 p5.14 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss 388-pin p-bga package pin configuration (top view) for tc11ib
tc11ib data sheet 6 v2.3, 2003-11 table 1 pin definitions and functions symbol pin in out pu/ pd 1) functions p0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.11 p0.12 p0.13 p0.14 p0.15 k1 l3 l2 l1 m1 m2 m3 m4 n1 n2 n3 p1 p2 p3 r1 r2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pub pub pub pub ? ? ? ? puc pdc pdc puc puc puc puc puc port 0 port 0 serves as 16-bit gener al purpose i/o port, which is also used as input/outp ut for the general purpose timer units (gptu0 & gptu1) gptu0_io0 gptu0 i/o line 0 gptu0_io1 gptu0 i/o line 1 gptu0_io2 gptu0 i/o line 2 gptu0_io3 gptu0 i/o line 3 gptu0_io4 gptu0 i/o line 4 gptu0_io5 gptu0 i/o line 5 gptu0_io6 gptu0 i/o line 6 gptu0_io7 gptu0 i/o line 7 gptu1_io0 gptu1 i/o line 0 gptu1_io1 gptu1 i/o line 1 gptu1_io2 gptu1 i/o line 2 gptu1_io3 gptu1 i/o line 3 gptu1_io4 gptu1 i/o line 4 gptu1_io5 gptu1 i/o line 5 gptu1_io6 gptu1 i/o line 6 gptu1_io7 gptu1 i/o line 7
tc11ib data sheet 7 v2.3, 2003-11 p1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p1.8 p1.9 p1.10 p1.11 p1.12 p1.13 p1.14 p1.15 a7 b7 c7 d7 a6 b6 c6 a5 b5 c5 d5 a4 c4 a3 b3 a2 i/o i/o i/o i/o o i/o i/o i/o o i o o i i o i i puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc port 1 port 1 serves as 16-bit gen eral purpose i/o port, which also is used as in put/output for the serial interfaces (ssc,asc,16x50) and mult imediacard interface (mmci) sclk ssc clock in put/output line mrst ssc master receive / slave transmit input/output mtsr ssc master transmit / slave receive input/output mmci_clk mmci clo ck output line mmci_cmd mmci command input/output line mmci_dat mmci data input/output line asc_rxd asc receiver input/output line asc_txd asc transmitter output line 16x50_rxd 16x50 receiver input line 16x50_txd 16x50 transmitter output line 16x50_rts 16x50 request to send output line 16x50_dcd 16x50 data carrier de tection input line 16x50_dsr 16x50 data set ready input line 16x50_dtr 16x50 data terminal ready output line 16x50_cts 16x50 clear to send input line 16x50_ri 16x50 ring indica tor input line table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 8 v2.3, 2003-11 p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 c18 a19 b18 a18 c17 b17 c16 b16 b10 c10 a9 b9 a8 c9 b8 c8 i/o o o o o o o o o i i i i i i i i ? ? ? ? ? ? ? puc pdc pdc puc pdc pdc pdc pdc pdc port 2 port 2 serves as 16-bit gener al purpose i/o port, which is also used as input/output for ethernet controller and multimediacard (mmci). mii_txd0 ethernet controller transmit data output line 0 mii_txd1 ethernet controller transmit data output line 1 mii_txd2 ethernet controller transmit data output line 2 mii_txd3 ethernet controller transmit data output line 3 mii_txer ethernet cont roller transmit error output line mii_txen ethernet controller transmit enable output line mii_mdc ethernet contro ller management data clock output line mmci_vdden mmci power supply enable output line mii_rxdv ethernet contro ller receive data valid input line mii_crs ethernet controll er carrier input line mii_col ethernet controller collision input line mii_rxd0 ethernet contro ller receive data input line 0 mii_rxd1 ethernet contro ller receive data input line 1 mii_rxd2 ethernet contro ller receive data input line 2 mii_rxd3 ethernet contro ller receive data input line 3 mii_rxer ethernet controll er receive error input line table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 9 v2.3, 2003-11 p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.14 p3.15 r3 r4 t1 t3 u1 u2 u3 v1 v2 v3 w2 w3 y1 y2 y3 y4 i/o i i i i i i i i i i i i i i i i ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 3 port 3 serves as 16-bit gener al purpose i/o port, which is also used as input for external interrupts. int0 external interrupt input line 0 int1 external interrupt input line 1 int2 external interrupt input line 2 int3 external interrupt input line 3 int4 external interrupt input line 4 int5 external interrupt input line 5 int6 external interrupt input line 6 int7 external interrupt input line 7 int8 external interrupt input line 8 int9 external interrupt input line 9 int10 external interrupt input line 10 int11 external interrupt input line 11 int12 external interrupt input line 12 int13 external interrupt input line 13 int14 external interrupt input line 14 int15 external interrupt input line 15 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 10 v2.3, 2003-11 p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 p4.8 p4.9 p4.10 p4.11 p4.12 p4.13 p4.14 p4.15 aa1 aa2 aa3 ab1 ab2 ab3 ab4 ac1 ac2 ac3 ad1 ad2 ae1 ae2 ad3 af2 i/o i i i i i i i i i/o i/o i/o i/o i/o i/o i/o i/o pdc pdc pdc pdc puc puc puc puc puc puc puc puc puc puc puc puc port 4 port 4 is used as general purpose i/o port, 8 pins of which (p4.0 ~ p4.7) also serv e as inputs for external interrupts. int16 external interru pt input line 16 int17 external interru pt input line 17 int18 external interru pt input line 18 int19 external interru pt input line 19 int20 external interru pt input line 20 int21 external interru pt input line 21 int22 external interru pt input line 22 int23 external interru pt input line 23 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 11 v2.3, 2003-11 p5 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 p5.8 p5.9 p5.10 p5.11 p5.12 p5.13 p5.14 p5.15 af1 ae3 ad4 ac5 af3 ae4 ad5 af4 ae5 ad6 ac7 af5 ae6 ad7 af6 ae7 i/o o i/o o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o o puc puc puc puc puc pdc puc puc pdc puc ? ? ? ? ? puc port 5 port 5 serves as 16-bit general purpose i/o port, 3 pins of which (p5.0, p5.2 and p5 .15) serve as output lines for multimediacard in terface (mmci) also. mmci_datrwmmci data direction indicator output line mmci_cmdrwmmci comman d direction indicator output line mmci_rod mmci command li ne mode indicator output line hdrst a1 i/o ? hardware reset input/reset indication output assertion of this bidirectio nal open-drain pin causes a synchronous reset of the chip through external circuitry. this pin must be driven for a minimum duration. the internal reset circuitry dr ives this pin in response to a power-on, hardware , watchdog, power-down wake-up reset and edram re set for a specific period of time. for a software rese t, activation of this pin is programmable. porst c3 i puc power-on reset input a low level on porst causes an asynchronous reset of the entire chip. porst is a fully asynchronous level sensitive signal. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 12 v2.3, 2003-11 nmi b2 i pub non-maskable interrupt input a high-to-low transition on th is pin causes a nmi-trap request to the cpu. cfg0 cfg1 cfg2 cfg3 k2 k3 j1 j2 i i i i pdc pdc puc puc operation configuration inputs the configuration inputs de fine the boot options of the tc11ib after a hardware-inv oked reset operation. cpu clk c2 o puc clock output trst ae8 i pdc jtag module reset/enable input a low level at this pin rese ts and disables the jtag module. a high level e nables the jtag module. tck af7 i puc jtag module clock input tdi ad9 i puc jtag module serial data input tdo af8 o ? jtag module serial data output tms ad8 i puc jtag module state machine control input ocdse h2 i puc ocds enable input a low level on this pin during power-on reset (porst = 0) enables the on-c hip debug support (ocds). in addition, the leve l of this pin during power- on reset determines th e boot configuration. brkin h3 i puc ocds break input a low level on this pin caus es a break in the chip?s execution when the ocds is enabled. in addition, the level of this pin during power-on reset determines the boot configuration. brkout j3 o ? ocds break output a low level on this pin in dicates that a programmable ocds event has occurred. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 13 v2.3, 2003-11 ocds2 ps0 ocds2 ps1 ocds2 ps2 ocds2 ps3 ocds2 ps4 e3 d2 b1 e4 d3 o o o o o puc puc puc puc puc pipeline status signal outputs ocds2 pc0 ocds2 pc1 ocds2 pc2 ocds2 pc3 ocds2 pc4 ocds2 pc5 ocds2 pc6 ocds2 pc7 g1 f1 f2 e1 d1 f3 e2 c1 o o o o o o o o puc puc puc puc puc puc puc puc indirect pc a ddress outputs ocds2 brk0 ocds2 brk1 ocds2 brk2 g2 g3 g4 o o o puc puc puc break qualification lines outputs table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 14 v2.3, 2003-11 p_ad0 p_ad1 p_ad2 p_ad3 p_ad4 p_ad5 p_ad6 p_ad7 p_ad8 p_ad9 p_ad10 p_ad11 p_ad12 p_ad13 p_ad14 p_ad15 p_ad16 p_ad17 p_ad18 p_ad19 p_ad20 p_ad21 p_ad22 p_ad23 p_ad24 p_ad25 p_ad26 p_ad27 p_ad28 p_ad29 p_ad30 p_ad31 ad26 ae25 ad25 af25 ae24 af24 ad24 ae23 af23 ad23 ae22 ad22 af22 ac22 ae21 ad21 ae17 af17 ad17 ae16 ad16 af16 ad15 ae15 ae14 af14 ad14 ae13 ad13 ae12 ad12 af12 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pci interface address /d ata bus input / output lines pci interface address / data bus line 0 pci interface address / data bus line 1 pci interface address / data bus line 2 pci interface address / data bus line 3 pci interface address / data bus line 4 pci interface address / data bus line 5 pci interface address / data bus line 6 pci interface address / data bus line 7 pci interface address / data bus line 8 pci interface address / data bus line 9 pci interface address / data bus line 10 pci interface address / data bus line 11 pci interface address / data bus line 12 pci interface address / data bus line 13 pci interface address / data bus line 14 pci interface address / data bus line 15 pci interface address / data bus line 16 pci interface address / data bus line 17 pci interface address / data bus line 18 pci interface address / data bus line 19 pci interface address / data bus line 20 pci interface address / data bus line 21 pci interface address / data bus line 22 pci interface address / data bus line 23 pci interface address / data bus line 24 pci interface address / data bus line 25 pci interface address / data bus line 26 pci interface address / data bus line 27 pci interface address / data bus line 28 pci interface address / data bus line 29 pci interface address / data bus line 30 pci interface address / data bus line 31 p_par ad20 i/o ? pci interface parity input / output p_serr ae20 i/o ? pci interface system error input / output p_perr af20 i/o ? pci interface parity error input / output table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 15 v2.3, 2003-11 p_stop ac20 i/o ? pci interface stop input / output p_c/be0 p_c/be1 p_c/be2 p_c/be3 ac24 af21 af18 af15 i/o i/o i/o i/o ? ? ? ? pci interface command / byte enable inputs / outputs p_idsel ac15 i ? pci interface id select input p_clk33 af11 i ? pci interface clock input p_req ae11 o ? pci interface bus request output p_gnt ad11 i ? pci interface bus grant input p_devs el af19 i/o ? pci interface device se lect input / output p_trdy ad19 i/o ? pci interface target ready input / output p_fram e ad18 i/o ? pci interface frame input / output p_irdy ae18 i/o ? pci interface initiato r ready input / output p_lock ae19 i ? pci interface lock input p_inta ae10 o ? pci interface interrupt a output p_intb af10 o ? pci interface interrupt b output p_pme ac12 o ? pci interface power ma nagement event output mii_ txclk a11 i pdc ethernet controller transmit clock mii_txd[3:0] and mii_txen are driven off the rising edge of the mii_txclk by the core and sampled by the phy on the rising edge of the mii_txclk. mii_ rxclk c11 i pdc ethernet controller receive clock mii_rxclk is a continuous clock. its frequency is 25 mhz for 100 mbps operation, and 2. 5 mhz for 10mbps. mii_rxd[3:0], mii_rxdv and mii_exer are driven by the phy off the falling edge of mii_rxclk and sampled on the rising edge of mii_rxclk. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 16 v2.3, 2003-11 mii_ mdio a10 i/o pda ethernet controller ma nagement data input / output when a read command is be ing executed, data which is clocked out of t he phy will be pres ented on the input line. when the core is clocki ng control or data onto the mii_mdio line, the signal wi ll carry the information. cs0 cs1 cs2 cs3 cs4 cs5 cs6 ab24 ac26 ab25 aa24 y23 r26 p24 o o o o o o o puc puc puc puc puc puc puc ebu_lmb chip select output line 0 ebu_lmb chip select output line 1 ebu_lmb chip select output line 2 ebu_lmb chip select output line 3 ebu_lmb chip select output line 4 ebu_lmb chip select output line 5 ebu_lmb chip select output line 6 each corresponds to a pr ogrammable region. only one can be active at one time. csemu ac25 o puc ebu_lmb chip select out put for emulator region csglb a21 o puc ebu_lmb chip select global output csovl c20 o puc ebu_lmb chip select ou tput for overlay memory csfpi b20 i puc ebu_lmb chip select input for internal fpi bus for external master to sele ct ebu_lmb as target in the slave mode ebuclk n26 o ? ebu_lmb external bus clock output derived from lmbclk as equa l, half or one-fourth of the frequency. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 17 v2.3, 2003-11 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 l25 l24 k24 k25 j24 h24 g24 g23 k26 j26 j25 h26 h25 g26 g25 f26 f25 f24 e24 e23 d24 c25 c24 b24 e26 e25 d26 d25 c26 b26 b25 a25 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc ebu_lmb address / data bu s input / output lines ebu_lmb address / data bus line 0 ebu_lmb address / data bus line 1 ebu_lmb address / data bus line 2 ebu_lmb address / data bus line 3 ebu_lmb address / data bus line 4 ebu_lmb address / data bus line 5 ebu_lmb address / data bus line 6 ebu_lmb address / data bus line 7 ebu_lmb address / data bus line 8 ebu_lmb address / data bus line 9 ebu_lmb address / data bus line 10 ebu_lmb address / data bus line 11 ebu_lmb address / data bus line 12 ebu_lmb address / data bus line 13 ebu_lmb address / data bus line 14 ebu_lmb address / data bus line 15 ebu_lmb address / data bus line 16 ebu_lmb address / data bus line 17 ebu_lmb address / data bus line 18 ebu_lmb address / data bus line 19 ebu_lmb address / data bus line 20 ebu_lmb address / data bus line 21 ebu_lmb address / data bus line 22 ebu_lmb address / data bus line 23 ebu_lmb address / data bus line 24 ebu_lmb address / data bus line 25 ebu_lmb address / data bus line 26 ebu_lmb address / data bus line 27 ebu_lmb address / data bus line 28 ebu_lmb address / data bus line 29 ebu_lmb address / data bus line 30 ebu_lmb address / data bus line 31 bc0 bc1 bc2 bc3 m25 m26 l26 m24 i/o i/o i/o i/o puc puc puc puc ebu_lmb byte control line 0 ebu_lmb byte control line 1 ebu_lmb byte control line 2 ebu_lmb byte control line 3 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 18 v2.3, 2003-11 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 aa26 v24 w24 y24 y25 aa25 y26 w25 w26 v25 v26 u25 u24 u26 t26 t25 t24 r23 r24 r25 a24 b23 c23 d22 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc ebu_lmb address bus input / output lines ebu_lmb address bus line 0 ebu_lmb address bus line 1 ebu_lmb address bus line 2 ebu_lmb address bus line 3 ebu_lmb address bus line 4 ebu_lmb address bus line 5 ebu_lmb address bus line 6 ebu_lmb address bus line 7 ebu_lmb address bus line 8 ebu_lmb address bus line 9 ebu_lmb address bus line 10 ebu_lmb address bus line 11 ebu_lmb address bus line 12 ebu_lmb address bus line 13 ebu_lmb address bus line 14 ebu_lmb address bus line 15 ebu_lmb address bus line 16 ebu_lmb address bus line 17 ebu_lmb address bus line 18 ebu_lmb address bus line 19 ebu_lmb address bus line 20 ebu_lmb address bus line 21 ebu_lmb address bus line 22 ebu_lmb address bus line 23 rd ab26 i/o puc ebu_lmb read control line output in the master mode input in the slave mode. rd/wr n24 i/o puc ebu_lmb write control line output in the master mode input in the slave mode. wait c19 i/o puc ebu_lmb wait control line svm d20 o pub ebu_lmb supervisor mode output ale a20 o pdc ebu_lmb address latch enable output ras p25 o puc ebu_lmb sdram row address strobe output cas n25 o puc ebu_lmb sdram column address strobe output table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 19 v2.3, 2003-11 cke p26 o puc ebu_lmb sdram clock enable output mr/w c21 o puc ebu_lmb motorola-style read / write output hold c22 i puc ebu_lmb hold request input in external master mode: while hold is high, tricore is operating in normal mode (is owner of the exte rnal bus). a high-to-low transition indicates a hold request from an external master.tricore backs off the bus and activates hlda and goes into hold mode. a low-to-high transitions causes an exit from hold mode.tricore deactivates hlda and takes over the bus and enters the nor mal operation again. in external slave mode: while both hold and hlda are high, tricore is in hold mode, the external bus interface signals are tristated. when tricore is released out of hold mode (hlda =0) and has completely taken over control of the external bus, a low level at this pin requests tri- core to go into hold mode ag ain. but in any case tri- core will perform at leas t one external bus cycle before going into hold mode again. hlda a23 i/o puc ebu_lmb hold acknow ledge input / output in external master mode: output. high during normal operation.when tricore enters hold mode, it sets hlda to low after releasing the bus. on exit of hold mode, tricore first sets hlda to high and then goes onto the bus again (to avoid col- lisions). in external slave mode: input. a high-to-low transition at this pin releases tri- core from hold mode. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 20 v2.3, 2003-11 breq b22 o puc ebu_lmb bus request output in external master mode: high during normal operation.tricore activates breq earliest one clock cycle after activating hlda , if it has to perform an external bus access. if tricore has regained the bus, breq is set to high one clock cycle after deactivation of hlda . in external slave mode: this signal is high as l ong as tricore operates from internal memory. when it detects that an external access is required , it sets breq to low and waits for signal hlda to become low. breq will go back to high when the slave has ba cked off the bus after it was requested to go into hold mode. rmw ab23 i/o puc ebu_lmb read-modify- write signal line baa a22 o puc ebu_lmb burst addr ess advance output for advancing address in a burst flash access adv b19 o puc ebu_lmb burst flash address valid output aclk m23 o ? ebu_lmb additional clock output additional clock running eq ual, 1/2, 1/3 or 1/4 fre- quency of ebuclk cmdela y b21 i puc ebu_lmb command delay input for inserting delays betw een address and command. test mode ae9 i pdc test mode select input for normal operation of the tc11ib, th is pin should be connected to v ss . tm ctrl1 c15 i pub test mode control input 1 for normal operation of the tc11ib, th is pin should be connected to v ddp . tm ctrl2 c12 i pub test mode control input 2 for normal operation of the tc11ib, th is pin should be connected to v ddp . table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 21 v2.3, 2003-11 clk42 d12 i pdc test clock 42 mhz input for normal operation of the tc11ib, th is pin should be connected to v ss . pll96 ctrl b15 o ? test pll96 analog output for normal operation of the tc11ib, this pin must not be connected. pll42 ctrl b12 o ? test pll42 analog output for normal operation of the tc11ib, this pin must not be connected. xtal1 xtal2 a15 a14 i o ? ? oscillator/pll/clock gene rator input/output pins xtal1 is the input to the main oscill ator amplifier and input to the internal clo ck generator. xtal2 is the output of the main oscillat or amplifier circuit. for clocking the device from an external sour ce, xtal1 is driven with the clock sign al while xtal2 is left unconnected. for crystal oscillator operation xtal1 and xtal2 are connected to the crystal with the appropriate recommended oscillator circuitry. v ddosc b14 ?? main oscillator power supply (1.8v) v ssosc c14 ?? main oscillator ground v ddpll96 b13 ?? pll96 power supply (1.8v) v sspll96 a13 ?? pll96 ground v ddpll42 a12 ?? test pll42 power supply (1.8v) for normal operation of the tc11ib, this pin must not be connected. v sspll42 c13 ?? test pll42 ground for normal operation of the tc11ib, this pin must be connected to v ss . v lmuref a16 ?? lmu reference voltage this pin has to be connected to v ss v comref ad10 ?? comdram reference voltage this pin has to be connected to v ss v dddram a17, af13 ?? edram power supply (1.8v) table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 22 v2.3, 2003-11 v dd h1 w1 t2,b4 b11 d6,f4 d10 d17 d21 f23 k4 k23 u4 u23 aa4 aa23 ac6 ac10 ac17 ac21 ?? core and logic power supply (1.8v) table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 23 v2.3, 2003-11 v ddp d8, d11, d14, d16, d19, h4, h23, l4, l23, n4, p23, t4, t23, w4, w23, ac8, ac11, ac13, ac16, ac19 ?? ports power supply (3.3v) table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 24 v2.3, 2003-11 v ss d4 d9 d13 d18 d23 j4 j23 n23 p4,v4 v23 ac4 ac9 ac14 ac18 ac23 l11 to l16, m11 to m16, n11 to n16, p11 to p16, r11 to r16, t11 to t16 ?? ground n.c. d15, a26, ae26, af9, af26 ?? not connected these pins must not be connected. 1) refers to internal pull-up or pull-down devi ce connected and corresponding type. the notation ? ? ? indicates that the internal pull-up or pull-down device is not enabled. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc11ib data sheet 25 v2.3, 2003-11 parallel ports the tc11ib has 96 digita l input/output port lines, which are organized into six parallel 16-bit ports, port p0 to port p5 with 3.3v nominal voltage. the digital parallel ports can be all used as general purpos e i/o lines or they can perform input/output functions for th e on-chip peripheral units. an overview on the port-to- peripheral unit assign ment is shown in figure 4 . figure 4 parallel port s of the tc11ib mca04951 tc11ib parallel ports gpio3 gpio4 gpio5 g pio alternate functions external interrupts external interrupts mmci gpio1 gpio0 gpio2 gpio alternate functions ethernet / mmci asc / ssc / m m c i / 16x50 gptu0 / gptu1
tc11ib data sheet 26 v2.3, 2003-11 serial interfaces the tc11ib includes three seri al peripheral interface units: ? asynchronous/synchronous serial interface (asc) ? high-speed synchronous serial interface (ssc) ? asynchronous serial interface (16x50) asynchronous/synchr onous serial interface figure 5 shows a global view of the functional blocks of t he asynchronous/synchronous serial interface asc. figure 5 general block diag ram of the asc interfaces asc module communicates with the external world via one pair of i/o lines. the rxd line is the receive data inpu t signal (in synchronous mode also output). txd is the transmit output signal. clo ck control, address decoding, and interrupt service request control are managed outsid e the asc module kernel. the asynchronous/synchronous serial in terface provides serial communication between the tc11ib a nd other microcontrollers, microprocessors or external peripherals. the asc supports full-duplex asynch ronous communicati on and half-duplex synchronous communicati on. in synchronous mode, data is transmitted or received synchronous to a shift clock which is generated by the asc internally. in asynchronous mode, 8-bit or 9-bit data tran sfer, parity generation, and the number of stop bits can be selected. parity, framing, an d overrun error detection ar e provided to increase the reliability of data transfers. transmission and reception of data are double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-b it baud rate generator mcb04938 clock control address decoder interrupt control f asc asc module port control p1.6 / asc_rxd rxd txd p1.7 / asc _txd
tc11ib data sheet 27 v2.3, 2003-11 provides the asc with a separate serial clock signal that ca n be very accurately adjusted by a prescaler implemented as a fractional divider. features: full duplex asynchron ous operating modes ? 8- or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baudrate from 3 mbaud to 0.71 baud (@ 48 mhz clock) multiprocessor mode for automati c address/data byte detection loop-back capability support for irda data transmi ssion up to 115. 2 kbaud maximum half-duplex 8-bit sync hronous operating mode ? baudrate from 6 mbaud to 488.3 baud (@ 48 mhz clock) double buffered transmitter/receiver interrupt generation ? on a transmitter buffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buffer full condition ? on an error condition (fra me, parity, overrun error) fifo ? 8 bytes receive fifo (rxfifo) ? 8 bytes transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 9-bit fifo data width ? programmable receive/transm it interrupt trigger level ? receive and transmit fifo filling level indication ? overrun error generation two pin pair rxd/txd available at port 1
tc11ib data sheet 28 v2.3, 2003-11 high-speed synchronous serial interface figure 6 shows a global view of the functiona l blocks of the hi gh-speed synchronous serial interface ssc. figure 6 general block diag ram of the ssc interfaces the ssc module has three i/o lines, located at port 1. the ssc module is further supplied by separate cl ock control, interrupt control, address decoding, an d port control logic. the ssc supports full-duple x and half-duplex serial synch ronous communication up to 24 mbaud (@ 48 mhz module cloc k). the serial cl ock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift direction, cl ock polarity, and phase are programmable. this allows communication with spi-compa tible devices. transmission and reception of data are double-buffered. a 16-bit baud rate generator provides t he ssc with a separate serial clock signal. mcb04952 clock control address decoder interrupt control f ssc ssc module port control p1.2 / m tsr txd rxd txd rxd master slave slave sclk master p1.1 / m r st p1.0 / sc lk
tc11ib data sheet 29 v2.3, 2003-11 features: master and slave mode operation ? full-duplex or ha lf-duplex operation flexible data format ? programmable number of data bits: 2 to 16 bit ? programmable shift directio n: lsb or msb shift first ? programmable clock polarity: idle lo w or high state fo r the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock baud rate generation from 24 mbaud to 366.2 baud (@ 48 mhz module clock) interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) three-pin interface ? flexible ssc pin configuration
tc11ib data sheet 30 v2.3, 2003-11 asynchronous serial interface (16x50) the 16x50 is a universal asynchronous rece iver/transmitter (uart) which is fully prorammable.it supports word lengths from five to eight bi ts, an optional parity bit and one or two stop bits.if enable d, the parity can be odd, even or forced to a defined state. the 16x50 includes a 16-bit programmable baud rate generator and an 8-bit scratch register, together with two 16-b yte fifos -one for transmit an d one for receive. it has six modem control lines and su pports a diagnostic loop-back mode. an interrupt can be generated from any o ne of 10 sources. figure 7 shows a global view of the functional blocks of the asynchronous serial interface (16x50). figure 7 general block diagram of the 16x50 interface the 16x50 module communicates with the exte rnal world via five input and three output lines located at port 1. the 16x50 provides serial asynchronous re ceive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transm itter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digita l data systems. synchronization for the serial data stream is accomplished by adding start an d stops bits to the transmit data to form a data character (character orientated protocol). data integrity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly co mplex especially when manufactured on a single integrated silicon chip. the 16x50 represents such an integration with greatl y enhanced features. the 16x50 is an upward soluti on that provides 16 bytes of transmit and receive fifo memory, instead of 1 byte pr ovided in the 16c450. the 16 x50 is designed to work with high speed modems and shared network environments, that require fast data processing time. increased performance is realized in the 16x50 by the larger transmit and receive mcb04937 clock control address decoder interrupt control f 16x50 16x50 module port control p1.15 / 16x50_ri p1.14 / 16x50_cts p1.13 / 16x50_dtr p1.12 / 16x50_dsr p1.11 / 16x50_dcd p1.10 / 16x50_rts p1.9 / 16x50_txd p1.8 / 16x50_r xd
tc11ib data sheet 31 v2.3, 2003-11 fifo?s. this allows the exte rnal processor to handle more networking tasks within a given time. the 4 selectable levels of fifo trigger provided for maximum data throughput performance especi ally when operating in a mu lti-channel environment. the combination of the above greatly reduces the bandwidth requirem ent of the external controlling cpu, increases performanc e, and reduces power consumption. the 16x50 is capable of operation to 3 mbps with a 48 mhz clock input ( f 16x50 ). features: software upward compat ible with the ns16550a standard modem interface programmable word length , stop bits and parity programmable baud rate generator interrupt generation diagnostic loop-back mode scratch register automatic hardware/s oftware flow control programmable xon/xoff characters independent transmit and receive control fifo ? 16 byte transmit fifo ? 16 byte receive fifo with error flags ? four selectable receive fifo interrupt trigger levels
tc11ib data sheet 32 v2.3, 2003-11 general purpose timer units figure 8 shows a global view of al l functional blocks of t he two general purpose timer unit (gptu0 & gptu1) modules. figure 8 general block diagra m of the gptu interface each gptu module, gptu0 and gptu1, consis ts of three 32-bit timers designed to solve such application tasks as event timing, event counting , and event re cording. and each gptu module communicat es with the external world via eight i/o li nes located at port 1. mcb04943 clock control address decoder interrupt control f gptu0 gptu0 module port control p0.0 / gptu0_io0 p0.1 / gptu0_io1 p0.2 / gptu0_io2 p0.3 / gptu0_io3 p0.4 / gptu0_io4 p0.5 / gptu0_io5 p0.6 / gptu0_io6 p0.7 / gptu0_io7 sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 out0 out1 out2 out3 out4 out5 out6 out7 clock control address decoder interrupt control f gptu1 gptu1 module port control p0.8 / gptu1_io0 p0.9 / gptu1_io1 p0.10 / gptu1_io2 p0.11 / gptu1_io3 p0.12 / gptu1_io4 p0.13 / gptu1_io5 p0.14 / gptu1_io6 p0.15 / gptu1_io7 sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 out0 out1 out2 out3 out4 out5 out6 out7
tc11ib data sheet 33 v2.3, 2003-11 the three timers in each gptu module t0, t1, and t2, ca n operate independently from each other or can be combined: general features: all timers are 32-bit precision time rs with a maximum input frequency of f gptu . events generated in t0 or t1 can be used to trigger actions in t2 timer overflow or underfl ow in t2 can be used to clock either t0 or t1 t0 and t1 can be concatenat ed to form one 64-bit timer features of t0 and t1: each timer has a dedicated 32 -bit reload register with automatic relo ad on overflow timers can be split into indi vidual 8-, 16-, or 24-bit ti mers with individual reload registers overflow signals can be selected to generate service requests, pin output signals, and t2 trigger events two input pins can det ermine a count option features of t2: count up or down is selectable operating modes: ?timer ? counter ? quadrature counter (incremental/p hase encoded counter interface) options: ? external start/stop, on e-shot operation, timer clear on external event ? count direction control through software or an external event ? two 32-bit reload/capture registers reload modes: ? reload on overflow or underflow ? reload on external event: positive transit ion, negative transiti on, or both transitions capture modes: ? capture on external event: positive transition, nega tive transition, or both transitions ? capture and clear timer on external event: positive transition, negative transition, or both transitions can be split into tw o 16-bit counter/timers timer count, reload, capture, and trigger functions can be assigned to input pins. t0 and t1 overflow events can also be assign ed to these functions. overflow and underflow signal s can be used to trigger t0 and/or t1 and to toggle output pins t2 events are freely assignabl e to the servic e request nodes.
tc11ib data sheet 34 v2.3, 2003-11 multimediacard interface (mmci) the multimediacard interfac e module provides interfac e to multimediacard bus. it supports the full multimediacard bus protoc ol as defined in mu ltimediacard system specification version 1.3. figure 9 shows a global view of the mmci module with the module specific interface connections. figure 9 general block diag ram of mmci interface the mmci module communicates with external world via tw o io lines and five output lines which are located at port 1, 2 and 5. clock control, interrupt service and address decoding are managed outsid e the mmci module kernel. mmci handles the data transfer on cmd an d dat of the mmc bus. it performs the transfer from bit serial to byte parallel or vice versa and sustains a 16mbps data rate. to fulfil the mmc bus protocol, special bytes are modified via inserting start and stop bits or crc bits. a clock controller is implemented to divide th e clock to the necessary mmc bus clock frequency. features 3 line serial interface --- glueless interface to multimediacard bus pointer based data transfer block and sequent ial card access 16mhz multimediacard bus clock generation crc protection for the mult imediacard bus communication optional programming voltage control buffered data transfer power management data communication with a data rate up to 2 mbyte/s mcb04946 clock control address decoder interrupt control f mmci mmci module port control p5.15 / m m c i_r o d p5.2 / m m c i_c m d _r w p5.0 / m m c i_d at_r w p2.7 / m m c i_vd d en p1.5 / m m c i_d at p1.4 / m m c i_c m d p1.3 / m m c i_c lk
tc11ib data sheet 35 v2.3, 2003-11 ethernet controller the mac controller implements the ieee 802.3 and operates either at 100 mbps or 10 mbps. figure 10 shows a global view of the ethernet controller module with the module specific interface connections. figure 10 general block diagram of the ethernet controller the ethernet controller comprise s the following functional blocks: 1. media access controller (mac) 2. receive buffer (rb) 3. transmit buffer (tb) 4. data management unit in receive direction (dmur) 5. data management unit in transmit direction (dmut) mcb04942 port control p2.15 / mii_rxer fast fpi (m /s) p2.14 / mii_rxd[3] p2.13 / mii_rxd[2] p2.12 / mii_rxd[1] p2.11 / mii_rxd[0] p2.10 / mii_col p2.9 / m ii_c r s p2.8 / m ii_r xd v p2.6 / m ii_m d c p2.5 / m ii_txen p2.4 / m ii_txer p2.3 / m ii_txd [3] p2.2 / m ii_txd [2] p2.1 / m ii_txd [1] p2.0 / m ii_txd [0] mii_txclk mii_txclk m ii_td io mii mac ethernet controller rb tb dmur dmut
tc11ib data sheet 36 v2.3, 2003-11 rb as well as tb provid es on-chip data buffering whereas dmur and dmut perform data transfer from/to the shared memory. two interfaces are provided by the ethernet controller module: 1. mii interface for connectio n of ethernet phys via ei ghteen input / output lines 2. master/slave fpi bus interface for conn ection to the on-chi p system bus for data transfer as well as configuration. features media independent interface (mii) according to ieee 802.3 support 10 or 100 mbps mii-based physical devices. support full duplex ethernet. support data transfer between ethernet cont roller and com-dram. support data transfer between ethernet controll er and sdram via ebu. 256 x 32 bit receive buffer and transmit buffer each. support burst transfers up to 8 x 32 byte. media access controller (mac) 100/10-mbps operations full ieee 802.3 compliance station management signaling large on-chip cam (content addressable memory) full duplex mode 80-byte transmit fifo 16-byte receive fifo pause operation flexible mac control support support long packet mode and short packet mode pad generation media independent interface (mii) media independence. multi-vendor point of interoperability. support connection of mac layer and physical (phy) layer devices. capable of supportin g both 100 mb/s and 10 mb/s data rates. data and delimiters are synch ronous to clock references. provides independent four bit wide transmit and receive data paths. support connection of phy layer and station ma nagement (sta) devices. provides a simple management interface. capable of drivi ng a limited length of shielded cable.
tc11ib data sheet 37 v2.3, 2003-11 pci the pci interface module of the tc11ib basically is a bu s bridge between the on-chip fpi bus and the external pci bus of the system. the pci inte rface is fully compliant to pci local bus specif ication rev. 2.2. figure 11 shows a global view of the pci module with the module specif ic pin connections. figure 11 general block diag ram of the pci interface the pci-fpi bridge is able to execute a nu mber of various data transfers between the fpi bus and the pci bus. beside the standar d pci functions (confi guration transactions), there are two main types of transfers which the bridge supports. firstly, it will forward a transaction that any pc i initiator directs to the pci interface of t he tc11ib to the on-chip fpi bus. secondly the bridge w ill forward certain tr ansactions that a fpi master initiates on the fpi bus to the pci bu s. depending on configuratio n, these transfers may be a mcb04949 pci module p_ad[31:0] p_c/be[3:0] p_par p_serr p_perr p_stop p_devsel p_trdy p_frame p_irdy p_lock p_inta p_intb p_pme p_req p_gnt p_idsel p_clk33 fast fpi (m /s)
tc11ib data sheet 38 v2.3, 2003-11 single data or burst transfers on both pci an d fpi bus. in addition, the bridge is able to handle a direct data transfer between pci bus and fpi bus utilizing it ?s programmable dma channel. the dma channel can only be activated by a fp i master. in order to work as a pci host bridge on the pc i bus, the variety of pci trans actions issued by the bridge includes configuration transactions of type 0 and type 1 when acti ng as a pci master. features pci v2.2 compliant, 32 bit, 33 mhz multifunction device, suppor t both pci master/host functi ons. these functions can be activated by: ?tricore ? fast ethernet ? dma channel support burst transfer from pc i to comdram, sdram and lmu. support dma channel data tr ansfers between pci and fpi loading of pci configuration register s done by tricore via fpi bus access support pci command support card-bus. power management ? according to pci bus power managem ent interface specification v1.1 ? support multiple pci power ma nagement states d0, d1, d2, d3 cold ? pme#-signalling from fa st ethernet in d1, d2. pci reset ? all tristatable pci outputs of the bridge are set to ?trist ate? upon pci reset, compliant to pci local bus specification v2.2
tc11ib data sheet 39 v2.3, 2003-11 on-chip memories the tc11ib provides the fo llowing on-chip memories: program memory unit (pmu) with ? 24 kbytes scratch-pad code ram (sram) ? 8 kbytes instruction ca che memory (i-cache) data memory unit (dmu) with ? 24 kbytes scratch-pad data ram (sram) ? 8 kbytes data cach e memory (d-cache) 16 kbytes boot rom (brom) edram local memory unit (lmu) with ? 512 kbytes code/data memory comdram with ? 1mbytes code/data memory peripheral control processor (pcp) with ? 16 kbytes data memory (pcode) ? 4 kbytes parameter ram (pram)
tc11ib data sheet 40 v2.3, 2003-11 address map table 2 defines the specific segm ent oriented addr ess blocks of the tc11ib with its address range, size, an d pmu/dmu access view. table 3 shows the block address map of the segment 15 which in cludes on-chip peri pheral units and ports. table 2 tc11ib block address map seg- ment address range size description dmu acc. pmu acc. 0 ? 7 0000 0000 h ? 7fff ffff h 2 gb mmu/ fpi space via f_fpi via f_ fpi c a c h e d 8 8000 0000 h ? 8fff ffff h 256 mb external memory space mapped from segment 10 via lmb via lmb 9 9000 0000 h ? 9fdf ffff h 254 mb pci space mapped from segment 11 via f_fpi via f_fpi 9fe0 0000 h ? 9fef ffff h 1 mb comdram space mapped from segment 11 9ff0 0000 h ? 9fff ffff h 1 mb reserved ? ? 10 a000 0000 h ? afbf ffff h 252 mb external memory space via lmb via lmb n o n- c a c h e d afc0 0000 h ? afc7 ffff h 512 kb lmu space via lmb via lmb afc8 0000 h ? afff ffff h 3.5 mb reserved ? ? 11 b000 0000 h ? bfdf ffff h 254 mb pci space mappable into segment 9 via f_fpi via f_fpi bfe0 0000 h ? bfef ffff h 1 mb comdram space bff0 0000 h ? bfff ffff h 1 mb reserved ? ? 12 c000 0000 h ? c007 ffff h 512 kb local memory unit edram space via lmb via lmb c a c h e d c008 0000 h ? cfff ffff h 255.5 mb reserved ? ?
tc11ib data sheet 41 v2.3, 2003-11 13 d000 0000 h ? d000 5fff h 24 kb local data sc ratchpad memory (sram) dmu local via lmb non-cached d000 6000 h ? d3ff ffff h ~ 64 mb reserved ? ? d400 0000 h ? d400 5fff h 24 kb local code scratchpad memory (sram) via lmb pmu local d400 6000 h ? d7ff ffff h ~64 mb reserved ? ? d800 0000 h ? ddff ffff h 96 mb external memory space via lmb via lmb de00 0000 h ? deff ffff h 16 mb emulator memory space df00 0000 h ? dfff bfff h ~16 mb reserved ? ? dfff c000 h ? dfff ffff h 16 kb boot rom space via s_fpi via s_fpi 14 e000 0000 h ? e7ff ffff h 128 mb external memory space via lmb ? e800 0000 h ? e807 ffff h 512 kb local memory space mapped to lmb segment 12 ? e808 0000 h ? e83f ffff h 3.5 mb reserved e840 0000 h ? e840 7fff h 32 kb local data memory (sram) mapped to lmb segment 13 e840 8000 h ? e84f ffff h ~1 mb reserved e850 0000 h ? e850 7fff h 32 kb local code memory (sram) mapped to lmb segment 13 e850 8000 h ? efff ffff h ~123 mb reserved table 2 tc11ib block address map (cont?d) seg- ment address range size description dmu acc. pmu acc.
tc11ib data sheet 42 v2.3, 2003-11 note: accesses to address defined as ?reserved? in table 2 lead to a bus error. the exceptions are marked with 1) 15 f000 0000 h ? f00f ffff h 1 mb on-chip peripherals & ports via s_fpi via s_fpi non-cached f010 0000 h ? f017 ffff h 1) 512 kb reserved ? ? f018 0000 h ? f018 ffff h 64 kb comdram control registers via s_fpi via s_fpi f019 0000 h ? f03f ffff h 1) 2.4375 mb reserved ? ? f040 0000 h ? f04f ffff h 1 mb pci/fpi-bridge registers via f_fpi ? f050 0000 h ? f0ff ffff h ~11 mb reserved ? f100 0000 h ? f1ff ffff h 16 mb pci configuration space via f_fpi f200 0000 h ? f200 05ff h 6 x 256 b bcu0 and fast ethernet registers f200 0600 h ? f7e0 feff h ~94 mb reserved ? f7e0 ff00 h ? f7e0 ffff h 256 b cpu slave interface registers (cps) via f_fpi f7e1 0000 h ? f7e1 ffff h 64 kb core sfrs f7e2 0000 h ? f7ff ffff h 15 x 128 kb reserved ? f800 0000 h ? f87f ffff h 8 mb lmb peripheral space (ebu_lmb and local memory edram control registers) via lmb f880 0000 h ? ffff ffff h 120 mb reserved ? 1) any access to this area will result in unpredicted behaviors of ports. table 2 tc11ib block address map (cont?d) seg- ment address range size description dmu acc. pmu acc.
tc11ib data sheet 43 v2.3, 2003-11 table 3 block address map of segment 15 symbol description address range size scu system control unit f000 0000 h ? f000 00ff h 256 bytes pcisir pci software inte rrupt request f000 0100 h ? f000 01ff h 256 bytes bcu1 slow fpi bus control unit 1 f000 0200 h ? f000 02ff h 256 bytes stm system timer f000 0300 h ? f000 03ff h 256 bytes ocds on-chip debug support f000 0400 h ? f000 04ff h 256 bytes ? reserved f000 0500 h ? f000 05ff h ? gptu0 general purpose ti mer unit 0 f000 0600 h ? f000 06ff h 256 bytes gptu1 general purpose ti mer unit 1 f000 0700 h ? f000 07ff h 256 bytes asc async./sync. serial interface f000 0800 h ? f000 08ff h 256 bytes 16x50 asynchronous seri al interface f000 0900 h ? f000 09ff h 256 bytes ssc high-speed synchronous serial interface f000 0a00 h ? f000 0aff h 256 bytes mmci multimediacard interface f000 0b00 h ? f000 0bff h 256 bytes sru service request unit f000 0c00 h ? f000 0dff h 512 bytes ? reserved f000 0e00 h ? f000 27ff h ? p0 port 0 f000 2800 h ? f000 28ff h 256 bytes p1 port 1 f000 2900 h ? f000 29ff h 256 bytes p2 port 2 f000 2a00 h ? f000 2aff h 256 bytes p3 port 3 f000 2b00 h ? f000 2bff h 256 bytes p4 port 4 f000 2c00 h ? f000 2cff h 256 bytes p5 port 5 f000 2d00 h ? f000 2dff h 256 bytes ? reserved f000 2e00 h ? f000 3eff h ? pcp pcp registers f000 3f00 h ? f000 3fff h 256 bytes reserved f000 4000 h ? f000 ffff h ? pcp data memory (pram) f001 0000 h ? f001 0fff h 4 kbytes reserved f001 1000 h ? f001 ffff h ? pcp code memory (pcode) f002 0000 h ? f002 3fff h 16 kbytes ? reserved f002 4000 h ? f017 ffff h ? 1) com- dram comdram control registers f018 0000 h ? f018 ffff h 64 kbytes ? reserved f019 0000 h ? f03f ffff h ? 1)
tc11ib data sheet 44 v2.3, 2003-11 pci pci bridge configuration registers f040 0000 h ? f04f ffff h 1 mbytes ? reserved f050 0000 h ? f0ff ffff h ? pci_cs x(x=1,2) pci configuration space registers f100 0000 h ? f1ff ffff h 16 mbytes bcu0 fast fpi bus cont rol unit 0 f200 0000 h ? f200 00ff h 256 bytes ecu ethernet controller unit f200 0100 h ? f200 05ff h 1280 bytes ? reserved f200 0600 h ? f7e0 feff h ? cpu slave interface registers (cps) f7e0 ff00 h ? f7e0 ffff h 256 bytes reserved f7e1 0000 h ? f7e1 7fff h ? mmu f7e1 8000 h ? f7e1 80ff h 256 bytes reserved f7e1 8100 h ? f7e1 bfff h ? memory protection registers f7e1 c000 h ? f7e1 efff h 12 kbytes reserved f7e1 f000 h ? f7e1 fcff h ? core debug register (ocds) f7e1 fd00 h ? f7e1 fdff h 256 bytes core special function registers (csfrs) f7e1 fe00 h ? f7e1 feff h 256 bytes general purpose register (gprs) f7e1 ff00 h ? f7e1 ffff h 256 bytes ? reserved f7e2 0000 h ? f7ff ffff h ? ebu ebu_lmb external bus unit f800 0000 h ? f800 01ff h 512 bytes ? reserved f800 0200 h ? f800 03ff h ? lmu local memory unit f800 0400 h ? f800 04ff h 256 bytes ? reserved f800 0500 h ? f87f fbff h ? dmu local data memory unit f87f fc00 h ? f87f fcff h 256 bytes pmu local program memory unit f87f fd00 h ? f87f fdff h 256 bytes lcu lmb bus control unit f87f fe00 h ? f87f feff h 256 bytes lfi lmb to fpi bus bridge (lfi) f87f ff00 h ? f87f ffff h 256 bytes ? reserved f880 0000 h ? ffff ffff h ? 1) any access to this area will result in unpredicted behaviors of ports. table 3 block address map of segment 15 (cont?d) symbol description address range size
tc11ib data sheet 45 v2.3, 2003-11 note: accesses to address defined as ?reserved? in table 3 lead to a bus error.the exceptions are marked with 1) memory protection system the tc11ib memory protection system spec ifies the addressable range and read/write permissions of memory segments available to the currently executing task. the memory protection system controls the position and rang e of addressable segments in memory. it also controls the kinds of read and write operations allowed within addressable memory segments. any illegal memory acce ss is detected by the memory protection hardware, which then invokes the appropriate trap service ro utine (tsr) to handle the error. thus, the memory protec tion system protects critical system functions against both software and hardware errors. the memory protecti on hardware can also generate signals to the debug unit to facilitate tracing illegal memory accesses. in saf-t11ib-64d96, tricore supports two address spaces: the vi rtual address space and the physical address space. both address space are 4g b in size and divided into 16 segments with each segment being 256mb. the upper 4 bits of th e 32-bit address are used to identify the segment. virtual segments are number ed 0 - 15. but a virtual address is always translated into a physical addr ess before accessing memory. the virtual address is translated into a physical addr ess using one of two translation mechanisms: (a) direct translation, and (b ) page table entry (pte) based translation. if the virtual address belongs to the upper ha lf of the virtual address sp ace then the virt ual address is directly used as the physical add ress (direct translation). if the virtual addr ess belongs to the lower half of the address space, then th e virtual address is us ed directly as the physical address if the proce ssor is operating in physical mode (direct translation) or translated using a page table entry if the processor is operating in virtual mode (pte translation). these are managed by memory managem ent unit (mmu) memory protection is enforced using separate mechanisms for the two translation paths. protection for dir ect translation memory protection for addresse s that undergo direct transl ation is enforced using the range based protection that has been used in the previous genera tion of the tricore architecture. the range based protection mechanism provides support for protecting memory ranges from unautho rized read, write, or inst ruction fetch accesses. the tricore architecture provides up to four prot ection register sets with the psw.prs field controlling the selection of the protection register set. because the tc11ib uses a harvard-style memory architecture, each me mory protection register set is broken down into a data protection register set and a code protection register set. each data protection register set can specify up to four address ranges to receive particular protection modes. each code protection re gister set can specify up to two address ranges to receive partic ular protection modes.
tc11ib data sheet 46 v2.3, 2003-11 each of the data protecti on register sets and code protection register sets determines the range and protec tion modes for a separate memory area. each contains register pairs which determi ne the address ra nge (the data segment protection registers and code segment pr otection registers) and on e register (data protection mode register) which determines the me mory access modes wh ich apply to the specified range. protection for pte based translation memory protection for addre sses that undergo pte based tr anslation is enforced using the pte used for the address translation. the pte provides supp ort for protecting a process from unauthorized read, write, or in struction fetches by other processes. the pte has the following bits that are provided for th e purpose of protection: l xe (execute enable) enables in struction fetch to the page. l we (write enable) enables data writes to the page. l re (read enable) enables data reads from the page. furthermore, user-0 accesses to virtual ad dresses in the upper half of the virtual address space are disallowed when operating in virtual mo de. in physical mode, user- 0 accesses are disallowed only to segments 14 and 15. any user-0 access to a virtual address that is restri cted to user-1 or super-visor mo de will cause a virtual address protection (vap) trap in both the physical and virtual modes.
tc11ib data sheet 47 v2.3, 2003-11 on-chip bus system the tc11ib includes two bus systems: ? local memory bus (lmb) ? on-chip fpi bus (fast fpi and slow fpi) there are two bridges to in terconnect these three buse s. the lmb-to-fpi (lfi) interfaces the fast fpi bus to lmb bus. the fpi-to-fpi (ffi ) interfaces slow fpi bus to fast fpi bus. local memory bus (lmb) the local memory bus interconnects the memo ry units and function al units, such as cpu and lmu. the main target of the lmb bu s is to support devices with fast response times, optimized for speed. this allows t he dmu and pmu fast a ccess to local memory and reduces load on the fpi bus. the tricore system itself is loca ted on lmb bus. via external bus unit, it interconnects tc 11ib and external components. the local memory bus is a synchronous, pi pelined, split bus with variable block size transfer support. it supports 8,16,32 & 64 bits single be at transactions and variable length 64 bits bl ock transfers. key features the lmb provides the following features: synchronous, pipelined, multi-mast er, 64-bit high performance bus support multiple bus masters support split transactions support variable bl ock size transfer burst mode read/write to memories connect caches an d on-chip memory and fast fpi bus
tc11ib data sheet 48 v2.3, 2003-11 on-chip fpi bus the fpi bus interconnects the functional units of the tc11 ib, such as the pcp and on- chip peripheral compo nents. the fpi bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. the low setu p overhead of the fpi bus access protocol guarantees fast fpi bus acquisition, which is required for time-critical applications.the fpi bus is designed to sust ain high transfer rates. for example, a peak transfer rate of up to 800 mbytes/s can be achieved with a 100 mhz bus clock and 32- bit data bus. multiple data tr ansfers per bus arbitr ation cycle allow the fpi bus to operate at close to its peak bandwidth . via external bus unit (ebu ), fpi bus also interconnects the external compon ents to tc11ib. there are two fpi buses in tc11 ib, fast fpi bus and slow fp i bus. in order to improve the system performance, the peripherals are splitted into two fpi buses based on their performance. the fast fpi bus runs at a speed of 96 mhz where most of the high performance peripheral like comdram, pci- fpi, ethernet contro ller, lfi etc. are connected. the slow fpi bus runs at half speed of its fast counter part. and it is used to connect some standard peripherals. there is a fpi-fpi bridge between them to transfer data. each of fpi buses has it s own bus control unit (bcu). features supports multiple bus masters supports demultiplexed address/data operation address bus up to 32 bits and data buses are 64 bits wide data transfer types include 8-, 16-, 32- and 64 bit sizes supports burst transfer single- and multiple-data tran sfers per bus acquisition cycle designed to minimize em i and power consumption controlled by an bus control unit (bcu) ? arbitration of fpi bus master requests ? handling of bus error. ffi-bridge features supports single/block* data read/ write transactions (8/16/32 bit) supports fpi- read modify write transactions (rmw) internal fifo interfaces betw een fpi master and fpi slave. optimized for fpi-bus frequency ratios 2:1 special retry/abort functionality note: block transaction support depends on generic settings and the depth of the bridge internal read- and write data buffer.
tc11ib data sheet 49 v2.3, 2003-11 lfi the lmb-to-fpi interface (lfi) block provides the circuitry to inte rface (bridge) the fpi bus to the local memory bus (lmb). lfi features compatible with th e fpi 3.2 and lmb bus specification v2.4 supports burst/single transa ctions, from fpi to lmb. supports burst/single transa ctions, from lmb to fpi high efficiency and performance: ? fastest access across the bridge takes three cycles, using a bypass. ? there are no dead cycles on arbitration. acts as the default master on fpi side. supports abort, error a nd retry condition s on both sides of the bridge. supports fpi?s clock the same, or half, as the lmb?s clock frequency. lmb clock is shut when no transactions are issue to lfi from both buses and none are in process in the lfi to mi nimize the power consumption.
tc11ib data sheet 50 v2.3, 2003-11 lmb external bus unit the lmb external bus control unit (ebu_lmb) of the tc11ib is the inte rface between external resources, like memories and peri pheral units, and the internal resources connected to on-chip buse s if enabled. the basic structur e and external interconnections of the ebu are shown in figure 12 . figure 12 ebu struct ure and interfaces mcb04941 ebu_lmb ad[31:0] bc[3:0] a[23:0] rd rd/wr wait svm hlda breq ale ras cs[6:0] csemu csglb csovl cas cke mr/w rmw hold csfpi ebuclk baa adv aclk cmdelay 32 4 24 7 lmu lmb pmu dmu lfi mmu tricore fast fpi to peripherals ffi to peripherals and pcp slow fpi
tc11ib data sheet 51 v2.3, 2003-11 the ebu is mainly used for the following tw o operations: masters on lmb bus access exte rnal memories through ebu_lmb an external (off-chip) master access in ternal (on-chip) devi ces through fpi bus. the ebu controls all transactions required for these two operations and in particular handles the arbitration of the ex ternal bus between multi-masters. the types of external resour ces accessed by the ebu are: intel style peripherals (separate rd and wr signals) motorola style peripherals (mr/ w signals) roms, eproms static rams pc 100 sdrams (burst read/write ca pacity / multi-bank/page support) specific types of burst mode flashes (intel 28f800f3/28f160f3, amd 29bl162) special support for extern al emulator/debug hardware features support local memory bus (lmb 64-bit) support external bus frequency up to 96 mh z and internal lmb frequency up to 166 mhz. external bus frequency: lm b frequency =1:1 or 1:2 or 1:4 highly programmable access parameters support intel-and motorola-s tyle peripherals/devices support pc 100 sdram (b urst access, multibanki ng, precharge, refresh) support 16-and 32-bit sdram data bus and 64,128 and 256mbit devices support burst flash (intel 28f800f3/160f3,amd 29bl162) support multiplexed access (address &data on the same bus) when pc 100 sdram is not implemented support address alignment, external address space up to 64 mbytes. support data buffering: code pr efetch buffer, r ead/write buffer. external master arbitration compatible to c166 and other tricore devices 8 programmable address region s (1 dedicated for emulator) support little-and big-endian signal for controlli ng data flow of slow-memory buffer slave unit for external (off-chip) master to access de vices on fpi bus
tc11ib data sheet 52 v2.3, 2003-11 peripheral control processor the peripheral control pr ocessor (pcp) performs tasks that would normally be performed by the combinati on of a dma controller and its supporting cpu interrupt service routines in a traditio nal computer system. it could ea sily be considered as the host processor?s first line of defense as an interrupt-handling eng ine. the pcp can off- load the cpu from having to service time-cri tical interrupts. this provides many benefits, including: avoiding large interrupt-drive n task context-switching latenc ies in the host processor lessening the cost of inte rrupts in terms of processor register and memory overhead improving the responsiveness of interrupt service routines to data-capture and data- transfer operations easing the implementation of multitasking operating systems. the pcp has an architecture which efficiently supports dma type transactions to and from arbitrary devices and memory addr esses within the tc11ib and also has reasonable stand alone computational capabilities. the pcp is made up of severa l modular blocks as follows: pcp processor core code memory (pcode) parameter memory (pram) pcp interrupt control unit (picu) pcp service reque st nodes (psrn) system bus interface to the slow fpi bus the pcp is fully interrupt-drive n, meaning it is only activa ted through service requests; there is no main program running in the background as with a conventional processor.
tc11ib data sheet 53 v2.3, 2003-11 figure 13 pcp block diagram table 4 pcp instruction set overview instruction group description dma primitives efficient dma channel implementation load/store transfer data between pram or fpi memory and the general purpose registers, as well as move or exchange values between registers arithmetic add, subtrac t, compare and complement divide/multiply divide and multiply logical and, or, exclusive or, negate, mclr and mset shift shift right or left, ro tate right or left, prioritize bit manipulation set, clear, insert and test bits flow control jump conditionally, jump long, exi t, no operation miscellaneous debug mcb04784 pcp processor core pcp service req. nodes psrns pcp interrupt control unit picu parameter memory pram code memory pcode fpi-interface pcp interrupt arbitration bus cpu interrupt arbitration bus fpi bus
tc11ib data sheet 54 v2.3, 2003-11 system timer the stm within the tc11ib is designed for global system timing applications requiring both high precision and long range. th e stm provides the following features: free-running 56-bit counter all 56 bits can be read synchronously different 32-bit portions of the 56 -bit counter can be read synchronously driven by clock, f stm (identical with the system clock f sys = 48mhz). counting begins at power-on reset continuous operation is not affected by any reset cond ition except power-on reset the stm is an upward counter, running with the system clock fre quency. it is enabled per default after reset, and imme diately starts counting up. ot her than via reset, it is no possible to affect the contents of the timer during normal operation of the application, it can only be read, but no t written to. depen ding on the implementation of the clock control of the stm, the timer can optionally be disabl ed or suspended for power-saving and debugging purposes via a clock control register. the maximum clock period is 2 56 f stm . at f stm = 48 mhz, for example, the stm counts 47.6 years before overfl owing. thus, it is capable of continuously timing the entire expected product life-time of a system without overflow. figure 14 block diagram of the stm module stm module 00 h cap tim6 tim5 tim4 tim3 tim2 tim1 tim0 00 h 55 47 39 31 23 15 7 56-bit system timer address decoder clock control enable / disable porst f stm mca04795
tc11ib data sheet 55 v2.3, 2003-11 watchdog timer the watchdog timer (wdt) provides a highly reliable and secure way to detect and recover from software or ha rdware failure. the wdt hel ps to abort an accidental malfunction of the tc11ib in a user-specified time period . when enabled, the wdt will cause the tc11ib system to be reset if the wdt is not servic ed within a user- programmable time period. the cpu must service the wdt with in this time interval to prevent the wdt from causing a tc11ib sys tem reset. hence, rout ine service of the wdt confirms that the system is functioning properly. in addition to this standa rd ?watchdog? function, the wdt incorporates the endinit feature and monitors its modi fications. a system-wide line is connected to the endinit bit implemented in a wdt control register, serv ing as an addi tional write-protection for critical registers (besides supervisor mode protection). a further enhancement in the tc11ib?s watchdog time r is its reset prewarning operation. instead of immedi ately resetting the device on the detection of an error, as known from standard watchdogs, the wdt first issues an non-maskable interrupt (nmi) to the cpu before finally resetti ng the device at a specified time period later. this gives the cpu a chance to save syst em state to memory for late r examination of the cause of the malfunction, an important aid in debugging. features 16-bit watchdog counter selectable input frequency: f sys /256 or f sys /16384 ( f sys = 48mhz) 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out a nd prewarning modes incorporation of the endinit bit an d monitoring of its modifications sophisticated password acce ss mechanism with fixed a nd user-definable password fields proper access always requires two wr ite accesses. the time between the two accesses is monitored by the wdt and limited. access error detection: invalid password (d uring first access) or invalid guard bits (during second access) trigger the watchd og reset generation. overflow error detection: an overflow of the counter tr iggers the watchdog reset generation. watchdog function can be disabled; acce ss protection and endi nit monitor function remain enabled. double reset detection: if a watchdog in duced reset occurs twice without a proper access to its control register in between, a severe system malfun ction is assumed and the tc11ib is held in reset until a power-o n reset. this prevents the device from being periodically reset if, for instance, connect ion to the external memory has been lost such that even syste m initialization coul d not be performed.
tc11ib data sheet 56 v2.3, 2003-11 important debugging support is provided through the re set prewarning operation by first issuing an nmi to the cp u before finally resetting the device after a certain period of time. system control unit the system control unit (scu) of the tc 11ib handles the system control tasks. all these system functions are tightly coupled, thus, they are conveni ently handled by one unit, the scu. the syst em tasks of the scu are: pll control ? pll_clc clock control register ? f sys = 96mhz clock generation. ? f sys = 48mhz clock generation. reset control ? generation of all in ternal reset signals ? generation of external hdrst reset signal ? generation of lmu edram reset signals boot scheme ? hardware booting scheme ? software booting scheme power management control ? enabling of severa l power-down modes ? control of the pll in power-down modes watchdog timer ocds2 trace port control selection between pc i and cardbus (pcmcia) standard compliance ffi bridge control device identification registers
tc11ib data sheet 57 v2.3, 2003-11 interrupt system an interrupt request can be serviced either by the cpu or by the peripheral control processor (pcp). these units are called ?ser vice providers?. interrupt requests are called ?service requests? rather than ?inte rrupt requests? in th is document because they can be serviced by eith er of the service providers. each peripheral in the tc11ib can generate service reque sts. additionally, the bus control unit, the debug unit, the pcp, and even the cpu itself can generate service requests to either of the two service prov iders. as shown in figure 15 , each tc11ib unit that can generate service reque sts is connected to one or multiple service request nodes (srn). each srn contains a servic e request control register mod_srcx, where ?mod? is the identifier of the service requesting unit and ?x? an optional index. two buses connect the srns with two interrupt control units, which handle interrupt arbitration among competing interru pt service requests, as follows: the interrupt control unit (icu) arbitr ates service requests for the cpu and administers the cpu inte rrupt arbitration bus. the peripheral interrupt cont rol unit (picu) arbitrates service requests for the pcp and administers the pcp interrupt arbitration bus. units which can generate service requests are: ? general purpose timer units (gptu 0 and gptu 1) with 8 srns each ? high-speed synchronous serial interfaces (ssc) with 3 srns ? asynchronous/synchronous serial interfaces (asc) with 4 srns ? asynchronous serial inte rface (16x50) with 1 srn ? pci with 33 srns ? ethernet controller with 9 srns ? multimediacard (mmci) with 1 srn ? external interrupt s with 24 srns ? bus control units (bcu0 and bcu1) with 1 srn each ? peripheral control processor (pcp) with 12 srns ? central processing unit (cpu) with 4 srns ? debug unit (ocds) with 1 srn the pcp can make service reque sts directly to itself (via the picu), or it can make service requests to th e cpu. the debug unit can genera te service requests to the pcp or the cpu. the cpu can make se rvice requests directly to itse lf (via the icu), or it can make service requests to the pcp. the cpu service re quest nodes are activated through software.
tc11ib data sheet 58 v2.3, 2003-11 figure 15 block diagram of th e tc11ib interrupt system mcb04944 8 srns 8 srns 8 gptu0 gptu1 3 srns 3 ssc 4 srns 4 asc 1 srn 1 16x50 33 srns 33 pci 9 srns 9 ethernet 1 srn 1 mmci 24 srns 24 external 1 srn 1 bcu0 1 srn 1 bcu1 1 srn 1 ocds service request nodes service requestors 8 8 2 3 4 4 1 1 33 33 9 9 1 1 24 24 1 1 1 1 1 1 pcp interrupt arbitration bus cpu interrupt arbitration bus 2 srns 2 srns interrupt control units 2 pipn pcp int. ack. ccpn 2 interrupt service providers 2 4 4 4 srns 4 pipn cpu ccpn int. ack. software interrupt icu picu 3 8 8 8 5 srns 3 srns 5 3 5 5 3 int. r eq. int. r eq.
tc11ib data sheet 59 v2.3, 2003-11 boot options the tc11ib booting schemes provides a number of different boot options for the start of code execution. table 5 shows the boot options avai lable in the tc11ib. 1) ssc/asc bootstrap loader is built in boot rom which provides a me chanism to load the startup program, which is executed after reset, via the ssc/asc interf ace. after successfully loade d, the startup program will be executed from the address at 0xc000 0004 h . table 5 boot selections ocdse brkin cfg [3] cfg [2:0] type of boot boot source initial pc value 1 1 x 000 b start directly in core scratchpad memory sram (only via sw reset) d400 0000 h not (000 or 100) start from boot rom boot rom, ssc bsl mode 1) (bootstrap loader) or asc bsl mode 1) dfff fffc h 0 100 b external memory as slave directly via ebu external memory (non-cached, cs0) a000 0000 h 1 100 b external memory as master directly via ebu 1 0 don?t care tri-state chip (deep sleep) ?? 0 1 0 100 b go to halt with ebu enabled as slave ?? 1 go to halt with ebu enabled as master all other combina- tions go to halt with ebu disabled 0 0 don?t care go to external emulator space ?de000000 h
tc11ib data sheet 60 v2.3, 2003-11 power management system the tc11ib power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. there are four powe r management modes: run mode idle mode sleep mode deep sleep mode table 6 describes these features of th e power management modes. besides these explicit software-control led power-saving modes, tc11ib supports automatic power-saving in that operating units, which are curre ntly not required or idle, are shut off automatica lly until their operati on is required again. table 6 power manageme nt mode summary mode description run the system is fu lly operational. al l clocks and periphera ls are enabled, as determined by software. idle the cpu clock is disabled, waiting fo r a condition to re turn it to run mode. idle mode can be entered by software wh en the processor has no active tasks to perform. all periphe rals remain powered and clocked. processor memory is accessible to peripherals. a rese t, watchdog timer event, a falling edge on the nmi pin, or any enabled interrupt event will return the system to run mode. sleep the system clock cont inues to be distributed on ly to those peripherals programmed to operate in sleep mode. interrupts from operating peripherals, the watchdog timer, a falling edge on the nmi pin, or a reset event will return the system to run mo de. entering this state requires an orderly shut-down controlled by t he power management state machine. deep sleep the system clock is shut off; only an external signal will restart the system. entering this stat e requires an orderly shut-down controlled by the power management state machine (pmsm).
tc11ib data sheet 61 v2.3, 2003-11 on-chip debug support the on-chip debug support of the tc11ib consists of four building blocks: ocds module in the tricore cpu ? on-chip breakpoint hardware ? support of an ex ternal break signal ocds module in the pcp ? special debug instruction fo r program execution tracing trace module of the tricore ? outputs 16 bits per cycle wi th pipeline status informati on, pc bus in formation, and breakpoint qualific ation information debugger interf ace (cerberus) ? provided for debug purposes of emulation tool vendors ? accessible through a jtag standard interface with dedicated jtag port pins figure 16 shows a basic block diagr am of the building blocks. . figure 16 ocds support basic block diagram mcb04947 cerberus & jtag trst tck tms tdi tdo jtag i/o lines tricore cpu ocds pcp ocds scu trace control 16 brkin brkout ocds2 ocds2 [15:0] ocdse fpi bus
tc11ib data sheet 62 v2.3, 2003-11 clock generation unit the clock generation unit in the tc11ib, shown in figure 17 , consists of an oscillator circuit and one phase-locke d loop (pll). the pll c an convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. the pll also has fail-safe logic that detects degenerate external cl ock behavior such as abnormal frequency deviations or a to tal loss of the external clo ck. it can execute emergency actions if it losses t he lock on the external clock. pl l can provide the 96mhz and 48mhz clocks. in general, the clock generation unit (cgu) is controlled through the system control unit (scu) module of the tc11ib. figure 17 clock generation unit block diagram 1 > mca04940 oscillator circuit xtal1 xtal2 f osc phase detect. vco n divider pll f vco 1 0 k:1 divider f sys = 96 mhz system_ clk lock detector osc_fail pll locked deep sleep ndiv [5:0] vco_ bypass kdiv [3:0] pll_ bypass system control unit scu register pll_clc mux 1 0 mux k:2 divider vco_ sel [1:0] f sys = 48 mhz system_ clk 1 0 mux pll_ 2en pll_ 2sel clock generation unit cgu
tc11ib data sheet 63 v2.3, 2003-11 recommended oscillator circuits figure 18 oscillator circuitries for the main oscillator of the tc11ib t he following external passive components are recommended: ? crystal: 12 mhz ? c1, c2: 10 pf a block capacitor between v ddosc and v ssosc is recommended, too. tc11ib oscillator mcs04948 tc11ib o scilla to r v ddosc v ssosc c 1 12 mhz c 2 xtal1 xtal2 v ddosc v ssosc xtal1 xtal2 external clock signal
tc11ib data sheet 64 v2.3, 2003-11 power supply the tc11ib provides an ingenious power supp ly concept in order to improve the emi behavior as well as to minimize th e crosstalk within on-chip modules. figure 19 shows the tc11ib?s power supply conc ept, where certain logic modules are individually supplied wi th power. this concept improves the emi behavior by reduction of the noise cross coupling. figure 19 tc11ib po wer supply concept mcb04953 pcp memory dmu pmu comdram pci ports cpu & peripheral logic gpio ports (p0-p5) ebu ports pll osc lmu v dddram v ss v comref v ss v ddp (3.3 v) v ss v ddpll96 v sspll96 v ddosc v ssosc v ss v lmuref v ss v dddram v ss (1.8 v) v dd
tc11ib data sheet 65 v2.3, 2003-11 power sequencing during power-up, the reset pin porst has to be held active until both power supply voltages have reached at l east their minimum values. while powering up (rising of the supply voltages from 0v to their regular operating values), it has to be ensured, that the co re power supply v dd reaches its operating value first, and then the gpio power supply v ddp . during the rising ti me of the core power supply it must be en sured that 0 < v dd - v ddp < 0.5v. during power-down, the core and gpio power supplies v dd and v ddp respectively, have to be switched off comple tely until all capacitances are discharged to zero, before the next power-up. note: the state of the pins are undef ined when only the port voltage v ddp is switched on.
tc11ib data sheet 66 v2.3, 2003-11 identification register values table 7 tc11ib identification registers short name address value scu_id f000 0008 h 0013 c002 h manid f000 0070 h 0000 1820 h chipid f000 0074 h 0000 8502 h rtid f000 0078 h 0000 0000 h bcu1_id f000 0208 h 0000 6a06 h stm_id f000 0308 h 0000 c002 h jpd_id f000 0408 h 0000 6302 h gptu0_id f000 0608 h 0001 c002 h gptu1_id f000 0708 h 0001 c002 h asc_id f000 0808 h 0000 4461 h 16x50_id f000 0908 h 0012 c001 h ssc_id f000 0a08 h 0000 4503 h mmci_id f000 0b08 h 0000 5b01 h pcp_id f000 3f08 h 0020 c002 h pci_id f040 0034 h 0001 15d1 h pci_subid f040 0038 h 0000 15d1 h pci_cs1_id f100 0000 h 0001 15d1 h pci_cs1_subid f100 002c h 0001 15d1 h pci_cs2_id f100 0100 h 0001 15d1 h pci_cs2_subid f100 012c h 0002 15d1 h bcu0_id f200 0008 h 0000 6a06 h cpu_id f7e0 ff18 h 0015 c004 h mmu_id f7e1 8008 h 0009 c002 h ebu_id f800 0008 h 0014 c003 h lmu_id f800 0410 h 0016 c001 h dmu_id f87f fc08 h 0008 c002 h pmu_id f87f fd08 h 000b c002 h lcu_id f87f fe08 h 000f c003 h lfi_id f87f ff08 h 000c c003 h
tc11ib data sheet 67 v2.3, 2003-11 absolute maximum ratings note: stresses above those listed under ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods ma y affect device reliability. during absolute maximum rati ng overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absol ute maximum ratings. parameter symbol limit values unit notes min. max. ambient temperature t a ? 25 85 c under bias storage temperature t st ? 65 150 c junction temperature t j ? 110 c under bias voltage on i/o supply pins with respect to ground ( v ss ) v ddp ?0.5 4.5 v voltage on core supply pins with respect to ground ( v ss ) v dd ?0.3 2.4 v voltage on pll supply pins with respect to ground ( v ss ) v ddpll ?0.3 2.4 v voltage on oscillator supply pins with respect to ground ( v ss ) v ddosc ?0.3 2.4 v voltage on edram supply pins with respect to ground ( v ss ) v dddram ?0.3 2.4 v voltage on any pi n with respect to ground ( v ss ) v in ? 0.5 4.5 v input current on any pin during overload condition i in -10 10 ma absolute sum of all input currents during overload condition i in ? |100| ma power dissipation p diss ?1.6w
tc11ib data sheet 68 v2.3, 2003-11 operating conditions the following operating conditions must no t be exceeded in orde r to ensure correct operation of the tc11ib. all pa rameters specified in the foll owing sections refer to these operating conditions, unless otherwise noticed. parameter interpretation the parameters listed in the following partly represent the characteristics of the tc11ib and partly its demand s on the system. to aid in interp reting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the tc11ib will provide sig nals with the respecti ve characteristics. sr ( s ystem r equirement): the external system must prov ide signals with the respecti ve characteristics to the tc11ib. parameter symbol limit values unit notes min. max. supply voltage v ddp 3.0 3.6 v i/o supply v dd 1.71 1.89 v core supply v ddpll 1.71 1.89 v pll supply v ddosc 1.71 1.89 v oscillator supply v dddram 1.71 1.89 v edram supply ground voltage v ss 0v ambient temperature under bias t a ? 25 85 c cpu clock f cpu ?96mhz external load capacitance c l ?50pf
tc11ib data sheet 69 v2.3, 2003-11 dc characteristics dc-characteristics v ss = 0 v; t a = -25 c to +85 c parameter symbol limit va lues unit test condition min. max. gpio pins, dedicated pins and ebu pins input low voltage v il sr ? 0.8 v input high voltage v ih sr 2.0 ? v output low voltage v ol cc ? 0.4 v output high voltage v oh cc 2.4 ? v pull-up current 1) i pub cc ? 37 ? 12 a v in = 0v i puc cc ? 12 ? 2 a v in = 0v pull-down current 2) i pda cc 55 220 a v in = v ddp i pdc cc 2 14 a v in = v ddp input leakage current 3) i oz2 cc ? 1 a0 < v in < v ddp pin capacitance 4) c io cc ? 10 pf pci pins input low voltage v ilp sr ? 0.5 0.3 v ddp v input high voltage v ihp sr 0.5 v ddp v ddp + 0.5 v output low voltage v olp cc ? 0.1 v ddp v i olp = 1500 a output high voltage v ohp cc 0.9 v ddp ?v i ohp = ? 500 a input pull-up voltage 5) v ipu cc 0.7 v ddp ? input leakage current 6) i il cc ? 10 a0 < v in < v ddp pme input leakage 7) i off cc ? 1 a v in 3.6v v dd off or floating input pin capacitance 8) c in cc ? 10 pf clk pin capacitance c clk cc 5 12 pf
tc11ib data sheet 70 v2.3, 2003-11 idsel pin capacitance 9) c idsel cc?8pf pin inductance l pin cc ? 20 nh oscillator pins input low voltage at xtal1 v ilx sr -0.3 0.3 v ddosc v input high voltage at xtal1 v ihx sr 0.7 v ddosc 2.4 v notes: 1) the current is applicable to the pins, for wh ich a pull up has been specified. refer to table 1 . i pu x refers to the pull up current for type x . 2) the current is applicable to the pins, for which a pull down has been specified. refer to table 1 . i pd x refers to the pull down current for type x . 3) pins with internal pull up or pull down are not included. 4) not 100% tested, guaranteed by design characterization. 5) this specification is guaranteed by design. it is the minimum voltage to which pull up resistors are calculated to pull a floated network. applications sensitive to stat ic power utilization must assu re that the input buffer is conducting minimum current at this input voltage. 6) input leakage currents include high impedance output leaka ge for all bi-directional buffers with tristate outputs. 7) this input leakage is the maximum allowable leakage into the pme open drain driver when power is removed from vdd of the component. this assumes that no event has occurred to cause the device to attempt to assert pme . 8) absolute maximum pin capacitance for a pci input is 10pf (except for clk). exceptions are granted to motherboard-only devices up to 16pf. 9) lower capacitance on this input-only pin allo ws for non-resistive coupling to ad[xx]. dc-characteristics(cont?d) v ss = 0 v; t a = -25 c to +85 c parameter symbol limit va lues unit test condition min. max.
tc11ib data sheet 71 v2.3, 2003-11 power supply current parameter symbol limit values unit test conditions typ. 1) 1) typical values are measured at 25c, cpu clock at 96mhz and nominal supply voltage, i.e. 3.3v for v ddp and 1.8v for v dd , v ddpll , v ddosc and v dddram . these currents are measured usi ng a typical application pattern. the power consumption of modules can increase or decrease using other application programs. the pll is bypassed while pci and mmci modules are inactive. max. active mode supply current i dd 481.9 629 ma sum of i dds 2) 2) these power supply currents are defined as the sum of all currents at the v dd power supply lines: v dd + v ddp + v dddram + v ddpll + v ddosc 412.9 519 ma i dd at v dd 3) 3) this measurement includes the tricore and logic power supply lines. 44.0 60 ma i dd at v ddp 25.0 50 ma i dd at v dddram idle mode supply current i id 213.0 308 ma sum of i dds 2)4) 4) cpu is in idle state, input clock to all peripherals are enabled, 195.8 259 ma i dd at v dd 3)4) 6.5 20 ma i dd at v ddp 4) 10.7 29 ma i dd at v dddram 4) sleep mode supply current i sl 195.4 288 ma sum of i dds 2)5)6) 5) input clock to all pe ripherals are disabled. 6) the values are not subject to production test - verified by characterization only. 178.2 239 ma i dd at v dd 3)5)6) 6.5 20 ma i dd at v ddp 5)6) 10.7 29 ma i dd at v dddram 5)6) deep sleep mode supply current i ds 11.2 69 ma sum of i dds 2)7) 7) clock generation is di sabled at the source. 6.7 41 ma i dd at v dd 3)7) 0.3 10 ma i dd at v ddp 7) 4.2 18 ma i dd at v dddram 7)
tc11ib data sheet 72 v2.3, 2003-11 ac characteristics (operating conditions apply) figure 20 input/output wa veforms for ac tests - for gpio, dedicated and ebu pins 2.0v 0.8v test points 2.0v 0.8v 2.4v 0.4v ac inputs during testing are driven at 2.4v for a logic ?1? and 0.4v for a logic ?0?. timing measurements are made at v ihmin for a logic ?1? and v ilmax for a logic ?0?.
tc11ib data sheet 73 v2.3, 2003-11 input clock timing (operating conditions apply) figure 21 input clock timing parameter symbol limits unit min max oscillator clock frequency with pll f osc sr 12 mhz input clock frequency driving at xtal1 with pll f oscdd sr 12 mhz input clock high time t 1 sr 37.5 ? ns input clock low time t 2 sr 37.5 ? ns input clock rise time t 3 sr ? 4.1 ns input clock fall time t 4 sr ? 4.1 ns input clock at xtal1 t 4 v ihx t 3 t 1 v ilx t 2 t oscdd 0.5 v dd
tc11ib data sheet 74 v2.3, 2003-11 cpu clock timing (operating conditions apply; c l = 50 pf) figure 22 cpuclk timing parameter symbol limits unit min max cpuclk period t cpuclk cc 10.4 ? ns cpuclk high time t 1 cc 3 ? ns cpuclk low time t 2 cc 4.5 ? ns cpuclk rise time t 3 cc ? 2.8 ns cpuclk fall time t 4 cc ? 2.2 ns cpuclk t 4 0.9 v dd t 3 t 1 0.1 v dd t 2 t cpuclk 0.5 v dd
tc11ib data sheet 75 v2.3, 2003-11 timing for edram refresh cycle (operating conditions apply; c l = 50 pf) figure 23 edram refresh cycle timing parameter symbol limits unit min max edram retention time t tret cc ? 16 ms lmu edram refresh cycle time t ref cc ? 1.6 s comdram edram refresh cycle time t ref cc ? 0.8 s refresh cycle time t ref refresh refresh edram access access cycle time
tc11ib data sheet 76 v2.3, 2003-11 timing for ebu_lmb clock outputs (operating conditions apply; c l = 50 pf) figure 24 ebu_lmb clock output timing parameter symbol limits unit min max ebuclk period 1) 1) lmb clock : ebuclk clock = 1:1 (ebu_ebucon.busclk = 00 h ). t 1 cc 10.4 ? ns ebuclk high time t 2 cc 4.5 ? ns ebuclk low time t 3 cc 3 ? ns ebuclk rise time t 4 cc ? 2.5 ns ebuclk fall time t 5 cc ? 2.5 ns aclk period 2) 2) lmb clock : aclk clock = 2:1 (ebu_bfcon.extclk = 01 h ). if ebu_bfcon.extclk = 10 h , the duty cycle is 33%, not 50%. t 6 cc 20 ? ns aclk high time t 7 cc 9 ? ns aclk low time t 8 cc 9 ? ns aclk rise time t 9 cc ? 3.5 ns aclk fall time t 10 cc ? 2.5 ns ebuclk / aclk 0.9 v dd 0.1 v dd t 1 (t 6 ) 0.5 v dd t 2 (t 7 ) t 3 (t 8 ) t 5 (t 10 ) t 4 (t 9 )
tc11ib data sheet 77 v2.3, 2003-11 timing for sdram access signals (operating conditions apply; c l = 30 pf) parameter symbol limits unit min max cke high from ebuclk t 1 cc ? 7.0 ns cke low from ebuclk t 2 cc ? 7.0 ns a(23:0) output valid from ebuclk t 3 cc ? 8.0 ns a(23:0) output hold from ebuclk t 4 cc 2.0 ? ns cs(6:0) low from ebuclk t 5 cc ? 7.0 ns cs(6:0) high from ebuclk t 6 cc ? 7.0 ns ras low from ebuclk t 7 cc ? 7.0 ns ras high from ebuclk t 8 cc ? 8.0 ns cas low from ebuclk t 9 cc ? 7.0 ns cas high from ebuclk t 10 cc ? 8.0 ns rd/wr low from ebuclk t 11 cc ? 7.5 ns rd/wr high from ebuclk t 12 cc ? 7.5 ns bc(3:0) low from ebuclk t 13 cc ? 7.0 ns bc(3:0) high from ebuclk t 14 cc ? 7.0 ns ad(31:0) output valid from ebuclk t 15 cc ? 7.7 ns ad(31:0) output hold from ebuclk t 16 cc 2.0 ? ns ad(31:0) input setup to ebuclk t 17 sr 0.6 ? ns ad(31:0) input hold from ebuclk t 18 sr 3.8 ? ns
tc11ib data sheet 78 v2.3, 2003-11 figure 25 sdram access timing t 6 t 9 t 13 t 14 column ebuclk a(23:0) csx ad(31:0) t 1 t 4 ebuclk cke t 3 ras c as rd/wr t 5 t 6 t 15 t 16 row data t 7 t 8 t 9 t 10 t 11 t 12 bc(3:0) t 13 t 14 data column ebuclk a(23:0) csx ad(31:0) ebuclk cke ras c as rd/wr t 17 t 18 data bc(3:0) data read access: write access: row t 10 t 2 t 4 t 3 (n-1) (0) (0) (n-1)
tc11ib data sheet 79 v2.3, 2003-11 timing for burst flash access signals operating conditions apply; c l = 50 pf) note:wait signal is not characterized here because the tc11ib does not cover such cases. parameter symbol limits unit min max a(23:0) output valid from aclk t 1 cc ? 11.0 ns a(23:0) output hold from aclk t 2 cc 2.0 ? ns cs(6:0) low from aclk t 3 cc ? 9.0 ns cs(6:0) high from aclk t 4 cc ? 9.0 ns adv low from aclk t 5 cc ? 10.0 ns adv high from aclk t 6 cc ? 10.0 ns baa low from aclk t 7 cc ? 10.0 ns baa high from aclk t 8 cc ? 10.0 ns rd low from aclk t 9 cc ? 12.0 ns rd high from aclk t 10 cc ? 10.0 ns ad(31:0) input setup to aclk t 11 sr 8.0 ? ns ad(31:0) input hold from aclk t 12 sr 1.0 ? ns
tc11ib data sheet 80 v2.3, 2003-11 figure 26 burst flash access timing a(23:0) csx ad(31:0) adv baa rd t 3 t 4 address t 5 t 6 t 7 t 8 t 10 data(0) aclk t 1 t 9 data(n-1) t 11 t 12 t 2
tc11ib data sheet 81 v2.3, 2003-11 timing for demultiplexed access signals (operating conditions apply; c l = 50 pf) parameter symbol limits unit min max ale low from ebuclk t 1 cc ? 8.0 ns ale high from ebuclk t 2 cc ? 8.0 ns a(23:0) output valid from ebuclk t 3 cc ? 8.0 ns a(23:0) output hold from ebuclk t 4 cc 2.0 ? ns cs(6:0) low from ebuclk t 5 cc ? 8.0 ns cs(6:0) high from ebuclk t 6 cc ? 8.0 ns mr/w low from ebuclk t 7 cc ? 8.0 ns mr/w high from ebuclk t 8 cc ? 8.0 ns rmw low from ebuclk t 9 cc ? 16.5 ns rmw high from ebuclk t 10 cc ? 16.5 ns rd low from ebuclk t 11 cc ? 8.0 ns rd high from ebuclk t 12 cc ? 8.0 ns rd/wr low from ebuclk t 13 cc ? 8.0 ns rd/wr high from ebuclk t 14 cc ? 8.0 ns cmdelay input setup to ebuclk t 15 sr 7.0 ? ns cmdelay hold from ebuclk t 16 sr 5.5 ? ns wait input setup to ebuclk t 17 sr 8.0 ? ns wait hold from ebuclk t 18 sr 5.5 ? ns bc(3:0) low from ebuclk t 19 cc ? 8.0 ns bc(3:0) high from ebuclk t 20 cc ? 8.0 ns ad(31:0) output valid from ebuclk t 21 cc ? 8.0 ns ad(31:0) output hold from ebuclk t 22 cc 2.0 ? ns ad(31:0) input setup to ebuclk t 23 sr 7.0 ? ns ad(31:0) input hold from ebuclk t 24 sr 3.5 ? ns
tc11ib data sheet 82 v2.3, 2003-11 figure 27 write access in demultiplexed access ebuclk a(23:0) csx ad(31:0) t 1 t 2 ebuclk ale t 3 mr/w rd/wr cmdelay t 5 t 6 t 21 t 22 address data t 7 t 15 t 16 t 13 t 4 wait t 14 bc(3.0) t 19 t 20 t 20 t 19 t 17 t 18
tc11ib data sheet 83 v2.3, 2003-11 figure 28 read access in demultiplexed access ebuclk a(23:0) csx ad(31:0) t 1 t 2 ebuclk ale t 3 mr/w rd cmdelay t 5 t 6 t 23 t 24 address data t 11 t 4 wait rmw t 9 t 12 t 17 t 18 bc(3:0) t 19 t 8 t 20 t 19 t 15 t 16 t 10 note: rmw signal is only available du ring read-modify-write access.
tc11ib data sheet 84 v2.3, 2003-11 timing for multiplexed access signals (operating conditions apply; c l = 50 pf) parameter symbol limits unit min max ale high from ebuclk t 1 cc ? 8.0 ns ale low from ebuclk t 2 cc ? 8.0 ns ad(31:0) output valid from ebuclk t 3 cc ? 8.0 ns ad(31:0) output hold from ebuclk t 4 cc 2.0 ? ns ad(31:0) input setup to ebuclk t 5 sr 7.0 ? ns ad(31:0) input hold from ebuclk t 6 sr 3.5 ? ns cs(6:0) low from ebuclk t 7 cc ? 8.0 ns cs(6:0) high from ebuclk t 8 cc ? 8.0 ns mr/w low from ebuclk t 9 cc ? 8.0 ns mr/w high from ebuclk t 10 cc ? 8.0 ns rmw low from ebuclk t 11 cc ? 16.5 ns rmw high from ebuclk t 12 cc ? 16.5 ns rd/wr low from ebuclk t 13 cc ? 8.0 ns rd/wr high from ebuclk t 14 cc ? 8.0 ns rd low from ebuclk t 15 cc ? 8.0 ns rd high from ebuclk t 16 cc ? 8.0 ns cmdelay input setup to ebuclk t 17 sr 7.0 ? ns cmdelay hold from ebuclk t 18 sr 5.5 ? ns wait input setup to ebuclk t 19 sr 6.0 ? ns wait hold from ebuclk t 20 sr 5.5 ? ns bc(3:0) low from ebuclk t 21 cc ? 8.0 ns bc(3:0) high from ebuclk t 22 cc ? 8.0 ns
tc11ib data sheet 85 v2.3, 2003-11 figure 29 write access in multiplexed access ebuclk ad(31:0) csx t 1 t 2 ebuclk ale t 3 mr/w rd/wr cmdelay t 7 t 8 address t 9 t 20 t 19 t 13 t 4 wait t 14 bc(3.0) t 21 t 22 t 22 t 21 data t 3 t 4 t 17 t 18
tc11ib data sheet 86 v2.3, 2003-11 figure 30 read access in multiplexed access ebuclk ad(31:0) csx t 1 t 2 ebuclk ale t 3 mr/w rd cmdelay t 7 t 8 address t 17 t 6 wait rmw t 16 t 18 bc(3:0) t 21 t 10 t 22 t 21 t 15 t 4 data t 5 t 19 t 20 t 11 t 12 note: rmw signal is available only duri ng read-modify-write access.
tc11ib data sheet 87 v2.3, 2003-11 timing for external bus arbitration signals (operating conditions apply; c l = 50 pf) parameter symbol limits unit min max hold input setup to ebuclk t 1 sr 6.0 ? ns hold input hold from ebuclk t 2 sr 5.5 ? ns hlda low from ebuclk t 3 cc ? 11.0 ns hlda high from ebuclk t 4 cc ? 11.0 ns hlda input setup to ebuclk t 5 sr 6.4 ? ns hlda input hold from ebuclk t 6 sr 5.5 ? ns breq low from ebuclk t 7 cc ? 9.5 ns breq high from ebuclk t 8 cc ? 9.5 ns cs(6:0) drive from ebuclk t 9 cc ? 8.0 ns cs(6:0) high-impedance from ebuclk t 10 cc ? 8.0 ns other signals high-i mpedance from ebuclk t 11 cc ? 8.0 ns other signals drive from ebuclk t 12 cc ? 8.0 ns
tc11ib data sheet 88 v2.3, 2003-11 figure 31 external bus arbitration timing ebuclk hlda ebuclk breq csx t 3 hold t 1 t 7 other signals t 9 t 11 t 2 t 4 t 8 t 9 t 12 t 10 ebuclk hlda ebuclk hold csx t 5 breq t 7 t 1 other signals t 12 t 8 t 6 t 2 t 10 t 11 t 9 external slave mode: external master mode:
tc11ib data sheet 89 v2.3, 2003-11 port timing (operating conditions apply; c l = 50 pf) figure 32 port timing parameter symbol limits unit min max port data valid from cpuclk 1) 1) port data is output with respect to the slow fpi cl ock at 48mhz. the cpuclk is used as a reference here since the slow fpi clock is not available as an external pin. port lines maintain its state for at least 2 cpu clocks. t 1 cc ? 14.0 ns cpuclk old state new state t 1 port lines s_fpi_clk
tc11ib data sheet 90 v2.3, 2003-11 timing for ethernet signals (operating conditions apply; c l = 50 pf) note: any other parameters which are not stated here , please refer to ansi/i eee std 802.3, section 22.3. parameter symbol limits unit min max etxclk period (10 mbps ethernet) t 1 sr 400.0 - ns etxclk high time (10 mbps ethernet) t 2 sr 140.0 260.0 ns etxclk low time (10 mbps ethernet) t 3 sr 140.0 260.0 ns etxclk period (100 mbps ethernet) t 1 sr 40.0 - ns etxclk high time (100 mbps ethernet) t 2 sr 14.0 26.0 ns etxclk low time ( 100 mbps ethernet) t 3 sr 14.0 26.0 ns erxclk period (10 mbps ethernet) t 1 sr 400.0 - ns erxclk high time (10 mbps ethernet) t 2 sr 140.0 260.0 ns erxclk low time (10 mbps ethernet) t 3 sr 140.0 260.0 ns erxclk period (100 mbps ethernet) t 1 sr 40.0 - ns erxclk high time (1 00 mbps ethernet) t 2 sr 14.0 26.0 ns erxclk low time (100 mbps ethernet) t 3 sr 14.0 26.0 ns erxd(3:0) input setup to erxclk t 4 sr 10.0 - ns erxd(3:0) input ho ld from erxclk t 5 sr - 10.0 ns erxdv input setup to erxclk t 4 sr 10.0 - ns erxdv input hold from erxclk t 5 sr - 10.0 ns erxer input se tup to erxclk t 4 sr 10.0 - ns erxer input hold from erxclk t 5 sr - 10.0 ns etxd(3:0) output valid from etxclk t 6 cc - 25.0 ns etxen output valid from etxclk t 6 cc - 25.0 ns etxer output valid from etxclk t 6 cc - 25.0 ns emdc clock period t 7 cc 150.0 - ns emdio input setup to em dc (sourced by sta) t 8 sr 10.0 - ns emdio input hold from emdc (sourced by sta) t 9 sr - 10.0 ns emdio output valid from emdc (sourced by phy) t 10 cc - 300.0 ns
tc11ib data sheet 91 v2.3, 2003-11 figure 33 ethernet timing t 1 etxclk erxclk erxd(3:0) erxdv erxer t 4 t 5 valid data etxd(3:0) etxen etxer t 6 valid data t 7 emdc emdio (sourced by sta) t 8 t 9 valid data t 10 emdio (sourced by phy) valid data t 2 t 3
tc11ib data sheet 92 v2.3, 2003-11 timing for multimediacard interface signals (operating conditions apply; c l = 50 pf) figure 34 multimediacard interface timing parameter symbol limits unit min max mmci.clk period t 1 cc 62.5 ? ns mmci.clk high time t 2 cc 28 ? ns mmci.clk low time t 3 cc 28 ? ns mmci.cmd_rw output va lid from mmci.clk t 4 cc ? 4.0 ns mmci.dat_rw output valid from mmci.clk t 4 cc ? 3.0 ns mmci.rod output va lid from mmci.clk t 4 cc ? 4.0 ns mmci.vdden output va lid from mmci.clk t 4 cc ? 2.0 ns mmci.cmd output va lid from mmci.clk t 4 cc ? 33 ns mmci.dat output va lid from mmci.clk t 4 cc ? 33 ns mmci.cmd input se tup to mmci.clk t 5 sr 12 ? ns mmci.dat input se tup to mmci.clk t 5 sr 10 ? ns mmci.cmd input hold from mmci.clk t 6 sr ? 2.0 ns mmci.dat input hold from mmci.clk t 6 sr ? 2.0 ns mmci.clk t 1 t 2 t 3 input t 5 valid data t 6 valid data t 4 output
tc11ib data sheet 93 v2.3, 2003-11 ssc master mode timing (operating conditions apply; c l = 50 pf) figure 35 ssc master mode timing parameter symbol limit values unit min. max. sclk clock frequency 1 / t sclk cc - 24 mhz sclk clock high time t 1 cc 18 - ns sclk clock low time t 2 cc 18 - ns sclk clock rise time t 3 cc - 11 ns sclk clock fall time t 4 cc - 11 ns mtsr low/high from sclk edge t 5 cc - 2.0 ns mrst setup to sclk edge t 6 sr 13 - ns mrst hold from sclk edge t 7 sr 7.5 - ns (con.po,con.ph = 00 or 11) 0.9 v dd 0.1 v dd t 1 t 2 t sclk t 3 t 4 data valid data valid t 2 t 1 t 5 state n-1 state n state n+1 0.9 v dd 0.1 v dd t 3 t 4 t 6 t 7 sclk (con.po,con.ph = 01 or 10) sclk mtsr mrst
tc11ib data sheet 94 v2.3, 2003-11 timing for jtag signals (operating conditions apply; c l = 50 pf) figure 36 tck clock timing parameter symbol limits unit min max tck clock period t tck cc 50 ? ns tck high time t 1 cc 10 ? ns tck low time t 2 cc 29 ? ns tck clock rise time t 3 cc ? 0.4 ns tck clock fall time t 4 cc ? 0.4 ns tck t 4 0.9 v dd t 3 t 1 0.1 v dd t 2 t tck 0.5 v dd
tc11ib data sheet 95 v2.3, 2003-11 figure 37 jtag timing parameter symbol limits unit min max tms setup to tck t 1 cc 7.85 ? ns tms hold to tck t 2 cc ? 1.0 ns tdi setup to tck t 1 cc 10.9 ? ns tdi hold to tck t 2 cc ? 1.0 ns tdo valid outpu t from tck t 3 cc ? 29.0 ns tdo high impedance to va lid output from tck t 4 cc ? 23.0 ns tdo valid output to high impedance from tck t 5 cc ? 26.0 ns tms tdi tck tdo t 1 t 2 t 1 t 2 t 4 t 3 t 5
tc11ib data sheet 96 v2.3, 2003-11 timing for ocds trace an d breakpoint signals (operating conditions apply; c l = 50 pf) figure 38 ocds trace signals timing parameter symbol limits unit min max brk_out valid from cpuclk t 1 cc ? 17.0 ns ocds2_status[4:0] valid from cpuclk t 1 cc ? 7.0 ns ocds2_indir_pc[7:0] valid from cpuclk t 1 cc ? 7.0 ns ocds2_brkpt[2:0] valid from cpuclk t 1 cc ? 7.0 ns pcp_pc[15:0] valid from cpuclk 1) 1) pcp trace signals are output with respect to the slow fpi clock at 48mhz. the cpuclk is used as a reference here since the slow fpi clock is not av ailable as an external pin. pcp tr ace signals maintain its state for at least 2 cpu clocks. t 2 cc ? 7.0 ns cpu trace signals cpuclk t 1 old state new state old state new state t 1 t 2 pcp trace signals note: cpu trace signals include brk_out , ocds2_status[4:0] , ocds2_indir_pc[7:0] and ocds_brkpt[2:0] . pcp trace signals include pcp_pc[15:0] .
tc11ib data sheet 97 v2.3, 2003-11 pci 33mhz, 3.3v signaling (operating conditions apply; c l = 10 pf) parameter symbol min. max. units test condition switching current high i oh (ac) -12v ddp ma 0 < v out 0.3v ddp 1) 1) refer to the v/i curves in figure 39 . switching current characteristics for req and gnt are permitted to be one half of that specified here; i.e., ha lf size output drivers may be used on these signals. this specification does not apply to clk and rst which are system outputs. ?switching current high? specifications are not relevant to serr , pme , inta , intb which are open drain outputs. -17.1(v ddp - v out ) ma 0.3v ddp < v out < 0.9v ddp 1) eqt?n 1 2) 2) equation 1 : i oh = (98/v ddp ) . (v out - v ddp ) . (v out + 0.4 v ddp ), where 0.7 v ddp < v out < v ddp 0.7v ddp < v out < v ddp 1) 3) (test point) - 32v ddp ma v out = 0.7v ddp 3) 3) maximum current requirements must be met as drivers pull beyond the first step voltage. equations defining these maximums (1 and 2) are provided with the respective diagrams in figure 40 . the equation-defined maximums should be met by design. in order to facilitat e testing, a maximum curren t test point is defined for each side of the output driver. switching current low i ol (ac) 16v ddp ma v ddp > v out 0.6v ddp 1) 26.7v out ma 0.6v ddp > v out > 0.1v ddp 1) eqt?n 2 4) 4) equation 2 : i ol = (256/v ddp ) . (v out ) . (v ddp - v out ), where 0 < v out < 0.18 v ddp 0.18v ddp > v out > 0 1) 3) (test point) 38v ddp ma v out = 0.18v ddp 3) low clamp current i cl -25 + (v in + 1)/(0.015) ma -3 < v in -1 high clamp current i ch 25 + (v in - v ddp -1)/ (0.015) ma v ddp +4 > v in v ddp +1 output rise slew rate slew r 1 4 v / ns 0.2v ddp - 0.6v ddp load 5) output fall slew rate slew f 1 4 v / ns 0.6v ddp - 0.2v ddp load 5)
tc11ib data sheet 98 v2.3, 2003-11 figure 39 v/i curves for 3.3v signaling figure 40 maximum ac waveforms for 3.3v signaling 5) this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition edge. the specified load (see figure 41 ) is optional; i.e., the designer may choose to meet this parameter with an unloaded output as per revision 2.0 of the pci local bus specification. however, adherence to both max. and min. parameters is required. rise slew rates does not apply to open drain outputs. 0.5 v ddp dc drive point 0.1 v ddp 0.6 v ddp test point 1.5 16 v ddp 64 v ddp current ( ma ) voltage ( v ) i oh = (98/ v ddp ) * ( v out - v ddp ) * ( v out + 0.4 v ddp ) where, v ddp > v out > 0.7 v ddp ac drive point - 0.5 - 12 v ddp - 48 v ddp 0.3 v ddp 0.9 v ddp v ddp test point dc drive point current ( ma ) voltage ( v ) v ddp i ol = (256/ v ddp ) * v out * ( v ddp - v out ) where, 0 < v out < 0.18v ddp pull up pull down ac drive point input buffer 3.3v supply v r evaluation setup 11ns (min) 4ns (max) + 7.1v - 3.5v 0v + 3.6v 7.1v p-to-p (minimum) 7.1v p-to-p (minimum) 62.5ns (16mhz) overvoltage waveform voltage source impedence r = 29 ? undervoltage waveform voltage source impedence r = 28 ?
tc11ib data sheet 99 v2.3, 2003-11 figure 41 load circuit for slew rate measurement pci clock specification (operating conditions apply; c l = 10 pf) figure 42 clock specification parameter symbol min. max. units notes clk cycle time t cyc 30 - ns 1) 1) in general, the pci component must work with an y clock frequency between nominal dc and 33 mhz. device operational parameters at frequencies under 16 mhz may be guaranteed by design rather than by testing. the clock frequency may be changed at any time during t he operation of the system so long as the clock edges remain ?clean? (monotonic) and the minimum cycle, high and low times are not violated. the clock may only be stopped in a low state. clk high time t high 11 - ns clk low time t low 11 - ns clk slew rate - 1 4 v/ns 2) 2) rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in figure 42 . output buffer pin 1/2 in. max. 10pf 1k ? v ddp 1k ? 0.6 v ddp 0.2 v ddp 0.3 v ddp 0.4 v ddp 0.5 v ddp 0.4v ddp p-to-p (min) t high t low
tc11ib data sheet 100 v2.3, 2003-11 pci 3.3v timing parameters ( operating conditions apply; c l = 10 pf ) parameter symbol min. max. units notes clk to signal valid delay - bused signals t val 211ns 1) 2) 3) 1) refer to figure 43 . 2) minimum times are evaluated with same load us ed for slew rate measurement (as shown in figure 41 ). maximum times are evaluated with the load circuits as illustrated in figure 45 . 3) req and gnt are point to point signals and have different output valid delay and input setup times compared to bused signals. gnt has a setup of 10 and req has a setup of 12. all other signals are bused. clk to signal valid delay - point to point t val(ptp) 212ns 1) 2) 3) float to active delay t on 2ns 1) 4) 4) for purposes of active/float timing measurements, the hi-z or "off" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. active to float delay t off 28 ns 1) 4) input setup time to clk - bused signals t su 7ns 3) 5) 6) 5) refer to figure 44 . 6) setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. input setup time to clk - point to point t su(ptp) 10, 12 ns 3) 5) input hold time from clk t h 0ns 5)
tc11ib data sheet 101 v2.3, 2003-11 measurement conditions figure 43 output timing measurement conditions figure 44 input timing me asurement conditions figure 45 load circuits for maximu m clock to signal valid delays clk output delay tri-state output v test v th v tl t val v step t on t off output current leakage current clk v th v tl t su input v test v th v tl v max v test inputs valid v test t h output buffer pin 1/2 in. max. 10pf 25 ? 25 ? 10pf 1/2 in. max. v ddp tval(max) rising edge tval(max) falling edge
tc11ib data sheet 102 v2.3, 2003-11 parameters for meas urement conditions symbol value units notes v th 0.6 v ddp v 1) 1) the input test is done with 0.1 v ddp overdrive. timing parameters must be met with no more overdrive than this. v tl 0.2 v ddp v 1) v test 0.4 v ddp v v step (rising edge) 0.285 v ddp v v step (falling edge) 0.615 v ddp v v max 0.4 v ddp v 2) 2) v max specifies the maximum peak-to-peak wavefo rm allowed for measuring input timing. production testing may use different voltage valu es, but must correlate results back to these parameters. input signal edge rate 1 v / ns
tc11ib data sheet 103 v2.3, 2003-11 package outline figure 46 p-bga-388-2 package sorts of packing package outlines for tubes, trays, etc. are containe d in data sheet ?package information? smd = surface mounted device plastic package, p-bga-388-2 (smd) (plastic ball grid array package)
http://www.infineon.com published by infineo n technologies ag infineon goes for business excellence ?business excellence means inte lligent approaches and clearly defined processes, wh ich are both constant ly under review and ultimately lead to go od operating results. better operating results and business excellence mean less idleness and wastefulness for al l of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.? dr. ulrich schumacher

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